Content Addressable Memory (CAM) Parity And Error Correction Code (ECC) Protection
First Claim
1. A memory system comprising:
- a row of content addressable memory (CAM) cells; and
a first non-CAM cell associated with the row of CAM cells.
1 Assignment
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Accused Products
Abstract
A memory system including a content addressable memory (CAM) array and a non-CAM array. The non-CAM array, which may share word lines with the CAM array, stores one or more error detection bits associated with each row of the CAM array. A state machine reads entries of the CAM array and corresponding error detection bits of the non-CAM array during idle cycles of the CAM array. Error detection logic identifies errors in the entries read from CAM array (using the retrieved error detection bits). If these errors are correctable, the error detection logic corrects the entry, and writes the corrected entry back to the CAM array (an updated set of error detection bits are also written to the non-CAM array). If these errors are not correctable, an interrupt is generated, which causes correct data to be retrieved from a shadow copy of the CAM array.
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Citations
34 Claims
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1. A memory system comprising:
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a row of content addressable memory (CAM) cells; and a first non-CAM cell associated with the row of CAM cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory system comprising:
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a content addressable memory (CAM) array that includes a plurality of CAM cells arranged in a plurality of rows and columns; and a memory array that includes a plurality of non-CAM cells, each associated with a corresponding one of the rows of the CAM array, wherein each of the non-CAM cells stores an error detection bit that is derived from an entry of the corresponding one of the rows of the CAM array. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method comprising:
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generating a first set of one or more error detection bits in response to a data value; storing the data value in a row of a content addressable memory (CAM) array; and storing the first set of one or more error detection bits in a location of non-CAM array, wherein the row of the CAM array is associated with the location of the non-CAM array. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification