HYBRID ELECTRONIC DESIGN SYSTEM AND RECONFIGURABLE CONNECTION MATRIX THEREOF

• US 20120110525A1
• Filed: 12/21/2010
• Published: 05/03/2012
• Est. Priority Date: 11/02/2010
• Status: Active Grant

• Current Assignee: Global UniChip Corp., Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Global UniChip Corp.
• Inventors: SU, Alan Peisheng
• Granted Patent: US 8,744,832 B2
• Time in Patent Office: Days
• US Class Current: 716/102
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

Claims

1. A hybrid electronic design system, comprising:

a virtual unit, including a plurality of proxies, a plurality of virtual components and a driver, wherein the virtual components being connected to the driver via the plurality of proxies;

a hybrid unit, including an emulating unit, a physical unit and a chip level transactor, wherein the chip level transactor being connected to the emulating unit and the physical unit; and

a communication channel for connecting to the driver of the virtual unit, and with the chip level transactor of the hybrid unit.

2. The hybrid electronic design system according to claim 1, wherein the hybrid unit comprises a first component transactor and a bus, the bus being connected to the chip level transactor via the first component transactor.

3. The hybrid electronic design system according to claim 1, wherein the hybrid unit comprises a second component transactor with a component, the component being connected to the chip level transactor via the second component transactor,

4. The hybrid electronic design system according to claim 3, wherein the component is selected from the group of consisting of a physical unit and an emulating unit.

5. The hybrid electronic design system according to claim 1, wherein the hybrid unit further comprises a reconfigurable connection matrix, including:

a configuration controller;

a chip level transactor;

a plurality of first component transactors and a plurality of buses, wherein the chip level transactor connecting to the configuration controller, the plurality of first component transactors and the plurality second component transactors, and the plurality of first component transactors connect the buses.

6. The hybrid electronic design system according to claim 1, wherein the emulating unit comprises a first connection matrix and a plurality of emulating components, and the emulating components connecting to the first connection matrix.

7. The hybrid electronic design system according to claim 6, wherein the hybrid unit further comprises:

a plurality of first component transactors; and

a plurality of buses, wherein the first connection matrix being connected to the plurality of first component transactors via the plurality of buses, and the first plurality of component transactors being connected to the chip level transactor.

8. The hybrid electronic design system according to claim 6, wherein the hybrid unit further comprises a plurality of second component transactors, the first connection matrix being connected to the chip level transactor via the plurality of second component transactors.

9. The hybrid electronic design system according to claim 6, wherein the hybrid unit further comprises a configuration controller, which connects to the chip level transactor and the first connection matrix.

10. The hybrid electronic design system according to claim 1, wherein the physical unit comprises:

a second connection matrix; and

a plurality of physical components, and the plurality of physical components connecting to the second connection matrix.

11. The hybrid electronic design system according to claim 10, wherein the hybrid unit further comprises:

a plurality of first component transactors; and

a plurality of buses, wherein the second connection matrix being connected to the plurality of first component transactors via the plurality of buses, and the first component transactors being connected to the chip level transactor.

12. The hybrid electronic design system according to claim 10, wherein the hybrid unit further comprises a plurality of second component transactors, the second connection matrix being connected to the chip level transactor via the plurality of second component transactors.

13. The hybrid electronic design system according to claim 10, wherein the hybrid unit further comprises a configuration controller, which connecting to the chip level transactor and the second connection matrix.

14. A reconfigurable connection matrix for connecting to a virtual unit, an emulating unit and a physical unit, wherein the virtual unit includes a driver, the emulating unit including a plurality of emulating components and a first connection matrix, the physical unit including a plurality of physical components and a second connection matrix, and the reconfigurable connection matrix, comprising:

a plurality of first component transactors;

a plurality of second component transactors;

a plurality of buses for connecting the first component transactors;

a configuration controller for connecting to the first connection matrix and the second connection matrix; and

a chip level transactor for connecting to the driver of the virtual unit, a plurality of first component transactors, a plurality of second component transactors and the configuration controller;

wherein the first connection matrix being connected to a plurality of buses and a plurality of second component transactors, the second connection matrix being connected to a plurality of buses and a plurality of second component transactors.

15. The reconfigurable connection matrix according to claim 14, wherein the configuration controller controls an operation of the first connection matrix and the second connection matrix in order to control the connection relation among the chip level transactor, the plurality of first component transactors, the plurality of second component transactors, the plurality of buses, the first connection matrix, and the second connection matrix.

16. The reconfigurable connection matrix according to claim 14, wherein the virtual unit comprises a plurality of virtual components, which being connected to the chip level transactor via the driver.