LOAD BALANCING WHEN ASSIGNING OPERATIONS IN A PROCESSOR

• US 20120110594A1
• Filed: 10/28/2010
• Published: 05/03/2012
• Est. Priority Date: 10/28/2010
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Venkataramanan, Ganesh, Lie, Sean, Talpes, Emil
• Application Number:
  US12/914,483
• Publication Number:
  US 20120110594A1
• Time in Patent Office: Days
• US Class Current: 718/105
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/505 considering the load

Abstract

A method and apparatus for assigning operations in a processor are provided. An incoming instruction is received. The incoming instruction is capable of being processed: only by a first processing unit (PU), only by a second PU or by either first and second PUs. The processing of first and second PUs is load balanced by assigning the received instructions capable of being processed by either the first and the second PUs based on a metric representing differential loads placed on the first and the second PUs.

Claims

1. A method for assigning operations in a processor comprising:

receiving an incoming instruction, the incoming instruction being capable of being processed;

only by a first processing unit (PU), only by a second PU or by either said first and said second PUs; and

load balancing the processing of said first and second PUs by assigning received instructions capable of being processed by either said first and said second PUs based on a metric representing differential loads placed on said first and said second PUs.

2. The method of claim 1 wherein the metric is compounded over at least one of three or four clock cycles.

3. The method of claim 1 further comprising:

receiving four incoming instructions in parallel during a clock cycle.

4. The method of claim 3 further comprising:

compounding the metric over the four incoming instructions.

5. The method of claim 1 further comprising:

assigning said instructions capable of being processed by either said first and said second PUs to said first PU on the condition that the metric indicates more said second PU assignments than said first PU assignments; and

assigning said instructions capable of being processed by either said first and said second PUs to said second PU on the condition that the metric indicates more said first PU assignments than said second PU assignments.

6. The method of claim 1 further comprising:

providing an indicator wherein said indicator indicates that said instructions capable of being processed by either said first and said second PUs is assigned to said second PU when the indicator is triggered and to said first PU when the indicator is not triggered.

7. A processor comprising:

a scheduler;

a decoder;

a first processing unit (PU);

a second PU; and

a renamer configured to receive an incoming instruction, the incoming instruction being capable of being processed;

only by a first processing unit (PU), only by a second PU or by either said first and said second PUs;

the renamer further configured to load balance the processing of said first and second PUs by assigning received instructions capable of being processed by either said first and said second PUs based on a metric representing differential loads placed on said first and said second PUs.

8. The processor of claim 7, wherein the metric is compounded over at least one of three or four clock cycles.

9. The processor of claim 7 further comprising circuitry configured to receive four incoming instructions in parallel during a clock cycle.

10. The processor of claim 9 further comprising circuitry configured to compound the metric over the four incoming instructions.

11. The processor of claim 7 further comprising circuitry configured to assign said instructions capable of being processed by either said first and said second PUs to said first PU on the condition that the metric indicates more said second PU assignments than said first PU assignments;

and assigning said instructions capable of being processed by either said first and said second PUs to said second PU on the condition that the metric indicates more said first PU assignments than said second PU assignments.

12. The processor of claim 7 further comprising circuitry configured to indicate that said instructions capable of being processed by either said first and said second PUs is assigned to said second PU when the indicator is triggered and to said first PU when the indicator is not triggered.

13. A computer system comprising:

a system memory; and

a processor coupled to the system memory wherein the processor comprises;

a scheduler;

a decoder;

a first processing unit (PU);

a second PU; and

a renamer configured to receive an incoming instruction, the incoming instruction being capable of being processed;

only by a first processing unit (PU), only by a second PU or by either said first and said second PUs;

the renamer further configured to load balance the processing of said first and second PUs by assigning received instructions capable of being processed by either said first and said second PUs based on a metric representing differential loads placed on said first and said second PUs.

14. The computer system of claim 13 wherein the metric is compounded over three or four clock cycles.

15. The computer system of claim 13 further comprising circuitry configured to assign four incoming instructions in parallel during a clock cycle.

16. The computer system of claim 15 further comprising circuitry configured to compound the metric over the four incoming instructions.

17. The computer system of claim 13 further comprising circuitry configured to assign said instructions capable of being processed by either said first and said second PUs to said first PU on the condition that the metric indicates more said second PU assignments than said first PU assignments;

and assigning said instructions capable of being processed by either said first and said second PUs to said second PU on the condition that the metric indicates more said first PU assignments than said second PU assignments.

18. The computer system of claim 13 further comprising circuitry to indicate that said instructions capable of being processed by either said first and said second PUs is assigned to said second PU when the indicator is triggered and to said first PU when the indicator is not triggered.

19. A computer-readable storage medium storing a set of instructions for execution by a general purpose computer to assign operations in a processor, the set of instructions comprising:

a receiving code segment for receiving an incoming instruction, the incoming instruction being capable of being processed;

only by a first processing unit (PU), only by a second PU or by either said first and said second PUs; and

a load balancing code segment for load balancing the processing of said first and second PUs by assigning received instructions capable of being processed by either said first and said second PUs based on a metric representing differential loads placed on said first and said second PUs.

20. The computer readable storage medium of claim 19, wherein the set of instructions are hardware description language (HDL) instructions used for the manufacture of a device.