Reduction of random telegraph signal (RTS) and 1/f noise in silicon MOS devices, circuits, and sensors

• US 20120112251A1
• Filed: 10/20/2011
• Published: 05/10/2012
• Est. Priority Date: 11/08/2010
• Status: Active Grant

• Current Assignee: Drake A. Miller, Leonard Forbes
• Original Assignee: Drake A. Miller, Leonard Forbes
• Inventors: Forbes, Leonard, Miller, Drake A.
• Granted Patent: US 8,513,102 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7855 with at least two independent gates

Abstract

The effects of random telegraph noise signal (RTS) or equivalently l/f noise on MOS devices, circuits, and sensors is described. Techniques are disclosed for minimizing this RTS and low frequency noise by minimizing the number of ionized impurity atoms in the wafer, substrate, well, pillar, or fin behind the channel of the MOS transistors. This noise reduction serves to reduce the errors in devices, sensors, and analog integrated circuits and error rates in digital integrated circuits and memories.

Claims

1. A method of reducing random telegraph signal (RTS) and l/f noise in active silicon MOS field effect devices, comprising the operations of:

defining an active silicon MOS field effect device on a substrate, said active silicon MOS field effect device having a width dimension equal to or less than 350 nm and a length dimension equal to or less than 350 nm; and

doping the conduction channel behind the gate electrode of said active silicon MOS field effect device to an ionized dopant atom concentration in the range of 10¹³ to 10¹⁵ atoms per cubic centimeter.

2. The method of claim 1 further comprising applying a forward bias the substrate-to-source junction of the active silicon MOS field effect device by a magnitude in the range of 0.3V to 0.7V.

3. The method of claim 2 wherein said applying a forward bias the substrate-to-source junction further comprises applying a forward bias of substantially 0.5V.

4. The method of claim 2 further comprising determining and setting the magnitude of V_GS−

V_T independently of a value of V_T.

5. The method of claim 1 wherein the active silicon MOS field effect device is one of an N-channel MOS transistor and a P-channel MOS transistor.

6. The method of claim 5 wherein said ionized dopant atoms are one of boron atoms and phosphorus atoms.

7. The method of claim 1 wherein the active silicon MOS field effect device is one of a vertical pillar MOS device and a fin-type MOS device.

8. The method of claim 7 further comprising biasing one gate of a plurality of gates to a magnitude of potential in the range of 0.0V and 5.0V.

9. A method of reducing random telegraph signal (RTS) and l/f noise in active silicon MOS field effect devices of nanometer size having as plurality of gates, comprising the operations of:

applying a forward bias to the substrate-to-source junction of the active silicon MOS field effect device by a magnitude of potential in the range of 0.3V to 0.7V; and

applying a bias to one gate electrode of the plurality of gates of the active silicon MOS field effect device to a magnitude of potential in the range of 0.0V and 5.0V.

10. The method of claim 9 further comprising doping the conduction channel behind the gate electrode of the active silicon MOS field effect device to an ionized dopant atom concentration in the range of 10¹³ to 10¹⁵ atoms per cubic centimeter.

11. The method of claim 9 wherein said applying a forward bias to the substrate-to-source junction further comprises applying a forward bias of substantially 0.5V.

12. The method of claim 9 further comprising determining and setting the magnitude of the gate-to-source bias, V_GS-V_T, independently of a value of V_T.

13. The method of claim 9 wherein the active silicon MOS field effect device is one of an N-channel MOS transistor and a P-channel MOS transistor.

14. The method of claim 13 wherein said ionized dopant atoms are one of boron atoms and phosphorus atoms.

15. The method of claim 9 wherein the active silicon MOS field effect device is one of a vertical pillar MOS transistor and a fin-type MOS transistor.

16. An active silicon MOS field effect transistor apparatus having a width dimension equal to or less than 350 nm and a length dimension equal to or less than 350 nm and reduced random telegraph signal (RTS) and l/f noise, the apparatus comprising:

a conduction channel behind a gate electrode of the active silicon MOS field effect transistor doped to an ionized dopant atom concentration in the range of 10¹³ to 10¹⁵ atoms per cubic centimeter; and

a substrate-to-source junction forward bias of a magnitude of potential in the range of 0.3V to 0.7V.

17. The apparatus of claim 16 wherein the active silicon MOS field effect transistor is one of an active pixel sensor, an imager, a digital integrated circuit of low error rate, a memory element of low error rate, a memory sense amplifier, and an analog integrated circuit of low offset voltage error.

18. The apparatus of claim 16 wherein said ionized dopant atoms are one of boron atoms and phosphorus atoms.

19. The apparatus of claim 18 wherein the active silicon MOS field effect transistor is one of a vertical pillar MOS transistor and a fin-type MOS transistor.

20. The apparatus of claim 16 further comprising a bias of one gate of a plurality of gates of the active silicon MOS field effect transistor to a magnitude of potential in the range of 0.0V and 5.0V.