TERMINATION STRUCTURE OF POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
First Claim
1. A termination structure of a power semiconductor device, the power semiconductor having an active region and a termination region, the termination region surrounding the active region, and the termination structure being disposed in the termination region, the termination structure comprising:
- a semiconductor substrate, having a first conductive type and a trench disposed in the termination region;
an insulating layer, partially filled into the trench and covering the semiconductor substrate, and a top surface of the insulating layer having a hole; and
a metal layer, disposed on the insulating layer and filled into the hole.
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Abstract
The present invention provides a termination structure of a power semiconductor device and a manufacturing method thereof. The power semiconductor device has an active region and a termination region. The termination region surrounds the active region, and the termination structure is disposed in the termination region. The termination structure includes a semiconductor substrate, an insulating layer and a metal layer. The semiconductor substrate has a trench disposed in the termination region. The insulating layer is partially filled into the trench and covers the semiconductor substrate, and a top surface of the insulating layer has a hole. The metal layer is disposed on the insulating layer, and is filled into the hole.
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Citations
26 Claims
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1. A termination structure of a power semiconductor device, the power semiconductor having an active region and a termination region, the termination region surrounding the active region, and the termination structure being disposed in the termination region, the termination structure comprising:
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a semiconductor substrate, having a first conductive type and a trench disposed in the termination region; an insulating layer, partially filled into the trench and covering the semiconductor substrate, and a top surface of the insulating layer having a hole; and a metal layer, disposed on the insulating layer and filled into the hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A termination structure of a power semiconductor device, the power semiconductor having an active region and a termination region, the termination region surrounding the active region, and the termination structure being disposed in the termination region, the termination structure comprising:
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a semiconductor substrate, having a conductive type and a trench; an insulating layer, covering the semiconductor substrate, and the trench being filled up with the insulating layer; and a metal layer, disposed on the insulating layer, and the metal layer comprising a contact plug penetrating through the insulating layer.
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12. A termination structure of a power semiconductor device, the power semiconductor having an active region and a termination region, the termination region surrounding the active region, and the termination structure being disposed in the termination region, the termination structure comprising:
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a semiconductor substrate, having a conductive type and a trench; and an insulating layer, covering the semiconductor substrate, and the trench being filled up with the insulating layer.
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13. A manufacturing method of a power semiconductor device, comprising:
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providing a semiconductor substrate, the semiconductor substrate having at least one first trench and a second trench, and the semiconductor substrate having an active region and a termination region, the first trench being disposed in the active region, the second trench disposed in the termination region, wherein the semiconductor substrate has a first conductive type; forming a gate structure in the first trench, wherein the gate structure comprises a first insulating layer and a gate conductive layer; forming a second insulating layer to cover the semiconductor substrate, the first trench being filled up with the second insulating layer, and the second insulating layer being filled into the second trench; removing the first insulating layer and the second insulating layer outside the first trench and the second trench to expose a part of the semiconductor substrate; forming a doped body region and a doped source region in the exposed semiconductor substrate, wherein the doped body region has a second conductive type, and the doped source region is disposed in the doped body region and has the first conductive type; forming an interlayer dielectric layer to cover the semiconductor substrate; and forming a source metal layer and a gate metal layer on the interlayer dielectric layer, so that the source metal layer is electrically connected to the doped source region, and the gate metal layer is electrically connected to the gate conductive layer. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification