POWER FACTOR CONTROLLER WITH ERROR FEEDBACK, AND A METHOD OF OPERATING SUCH A POWER FACTOR CONTROLLER

• US 20120112711A1
• Filed: 10/28/2011
• Published: 05/10/2012
• Est. Priority Date: 11/08/2010
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: PANSIER, Frans, ZHANG, Cheng, DEGEN, Peter Theodorus Johannes
• Granted Patent: US 9,712,047 B2
• Time in Patent Office: Days
• US Class Current: 323/205
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A power factor controller is disclosed, in which error feedback is provided my means of a parallel combination of at least two error feedback channels. By providing at least two error feedback channels, the stability associated with, for instance, a continuously integrated feedback loop with relatively long time constant, may be combined with a fast transient response associated with, for instance, a sample-and-hold error feedback.

A method of operating such a power factor controller is also disclosed.

Claims

1. A power factor controller comprising an error feed-back circuit for controlling an output of the power factor controller, wherein the error feedback circuit comprises a parallel arrangement of at least first error feedback channel and a second error feedback channel.

2. A power factor controller as claimed in claim 1, wherein the first error feedback channel comprises an integrator configured to integrate a difference between a signal indicative of an output of the power factor controller and a reference signal.

3. A power factor controller as claimed in claim 2, wherein the integrator is configured to be a continuous-time integrator.

4. A power factor controller as claimed in claim 1, wherein the second error feedback channel comprises an integrator configured to periodically integrate a difference between a signal indicative of an output of the power factor controller and a reference signal over a predetermined time interval.

5. A power factor controller as claimed in claim 4 adapted for operation with a mains supply and wherein the periodic integration has a periodicity associated with that of a mains half-cycle.

6. A power factor controller as claimed in claim 4, wherein the first error feedback channel is arranged to be sampled to provide a sample, and the sample provided to the second error feedback channel to determine an initial value for the integration of a difference between a signal indicative of an output of the power factor controller and a reference signal.

7. A power factor controller as claimed in an claim 1, wherein the second error feedback channel comprises a sample and hold circuit configured to periodically sample a difference between a signal indicative of an output of the power factor controller and a reference signal at a predetermined moment.

8. A power factor controller as claimed in claim 7 adapted for operation with a mains supply and wherein the periodic sampling has a periodicity associated with that of a mains half-cycle.

9. A power factor controller as claimed claim 8, wherein an output of the error feed-back circuit comprises the sum of an output of the first error feedback channel and an output of the second error feedback channel.

10. A power factor controller as claimed in claim 9, wherein the sum comprises a scaled version of the respective output of at least one of the first and second error feedback channels.

11. A power factor controller as claimed in claim 9, wherein the output of at least one of the first and second error feedback circuits includes an offset signal for adjusting a range of at least one of said outputs.

12. A switched mode power converter comprising a power factor controller as claimed in claim 1.

13. A method of providing an error feed-back signal in a power factor controller operating in voltage control mode, the method comprising providing a first channel error feedback signal by continuously integrating a difference between a signal indicative of an output of the power factor control and a reference signal, providing a second channel error feedback signal, and determining an error feedback signal from the first channel error feedback signal and the second channel error feedback signal.

14. The method of claim 13, wherein providing a second channel error feedback signal comprises periodically sampling a difference between a signal indicative of an output of the power factor control and a reference signal at a predetermined moment.

15. The method of claim 13, wherein providing a second channel error feedback signal comprises periodically integrating a difference between a signal indicative of an output of the power factor control and a reference signal over a predetermined time interval.