SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE

• US 20120113707A1
• Filed: 11/03/2011
• Published: 05/10/2012
• Est. Priority Date: 11/08/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TAKEMURA, Yasuhiko
• Granted Patent: US 8,902,637 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

Claims

1. A semiconductor memory device comprising:

a writing bit line;

a writing word line;

a reading bit line;

a reading word line;

a memory cell; and

an inverting amplifier circuit configured to supply an inverted and amplified potential of the reading bit line to the writing bit line,

wherein the memory cell comprises a writing transistor, a reading transistor, and a capacitor comprising a first electrode and a second electrode,

wherein a source of the writing transistor, a gate of the reading transistor, and the first electrode of the capacitor are connected to each other,

wherein a drain of the writing transistor is connected to the writing bit line,

wherein a gate of the writing transistor is connected to the writing word line,

wherein a drain of the reading transistor is connected to the reading bit line, and

wherein the second electrode of the capacitor is connected to the reading word line.

3. The semiconductor memory device according to claim 1 or 2,

wherein the writing transistor and the reading transistor are provided in different layers.

4. The semiconductor memory device according to claim 1 or 2,

wherein a kind of semiconductor used in the writing transistor and a kind of semiconductor used in the reading transistor are different from each other.

5. The semiconductor memory device according to claim 1 or 2,

wherein the inverting amplifier circuit is a flip-flop circuit.

6. The semiconductor memory device according to claim 1 or 2,

wherein the inverting amplifier circuit is an inverter.

7. A driving method of the semiconductor memory device according to claim 1, comprising the steps of:

pre-charging the drain of the writing transistor and the drain of the reading transistor to different potentials;

changing a potential of a wiring connected to the second electrode of the capacitor; and

outputting a potential whose phase is opposite to a phase of a potential of the drain of the reading transistor to the drain of the writing transistor with the inverting amplifier circuit.

2. A semiconductor memory device comprising:

a first bit line and a second bit line;

a first word line and a second word line;

a first memory cell and a second memory cell; and

an inverting amplifier circuit configured to supply an inverted and amplified potential of the second bit line to the first bit line or an inverted and amplified potential of the first bit line to the second bit line,

wherein each of the first memory cell and the second memory cell comprises a writing transistor, a reading transistor, and a capacitor comprising a first electrode and a second electrode,

wherein a source of the writing transistor of the first memory cell, a gate of the reading transistor of the first memory cell, and the first electrode of the capacitor of the first memory cell are connected to each other,

wherein a source of the writing transistor of the second memory cell, a gate of the reading transistor of the second memory cell, and the first electrode of the capacitor of the second memory cell are connected to each other,

wherein a drain of the writing transistor of the first memory cell is connected to the first bit line,

wherein a drain of the writing transistor of the second memory cell is connected to the second bit line,

wherein a gate of the writing transistor of the first memory cell is connected to the second word line,

wherein a gate of the writing transistor of the second memory cell is connected to the first word line,

wherein a drain of the reading transistor of the first memory cell is connected to the second bit line,

wherein a drain of the reading transistor of the second memory cell is connected to the first bit line,

wherein the second electrode of the capacitor of the first memory cell is connected to the first word line. and

wherein the second electrode of the capacitor of the second memory cell is connected to the second word line.

8. A driving method of the semiconductor memory device according to claim 2, comprising the steps of:

pre-charging the first bit line and the second bit line to different potentials;

changing a potential of the first word line; and

outputting a potential whose phase is opposite to a phase of a potential of the second bit line to the first bit line with the inverting amplifier circuit.