METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE
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Abstract
A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.
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Citations
48 Claims
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1-21. -21. (canceled)
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22. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region configured to inject charge into said floating body region to hold the state of said memory cell. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region configured to inject charge into said floating body region, wherein; said substrate region, said buried layer region, said floating body region, and either of said first or second regions form a silicon controlled rectifier device. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37)
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38. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; a buried layer region in electrical contact with said floating body region, below said first and second regions, spaced apart from said first and second regions; and a substrate region configured to inject charge into or extract charge out of said floating body region to hold said state of the memory cell. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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Specification