DUAL SHIFT REGISTER

• US 20120114092A1
• Filed: 01/19/2012
• Published: 05/10/2012
• Est. Priority Date: 07/03/2009
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: KIM, Hong Jae
• Granted Patent: US 8,238,512 B2
• Time in Patent Office: Days
• US Class Current: 377/69
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.

Claims

1-20. -20. (canceled)

21. A dual shift register comprising:

a first shift register configured to include a plurality of stages which sequentially output scan pulses using four clock signals with sequential and circular phases; and

a second shift register configured to include a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals,

wherein, each of the stages includes,

a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and

an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages, and

wherein the other stage of each stage pair includes a node controller configured to respond to the output signal from the scan direction controller and to control signals on first and second nodes, and wherein the output portion within the other stage of each stage pair is configured to respond to the signals on the first and second nodes and to generate the two sequential scan pulses using the two clock signals,

wherein the node controller includes,

wirings configured to independently charge the output signal of the scan direction controller into the first and second nodes;

a first active switching element connected between a first AC voltage line and a first common node;

a first switching element turned-on/off by the signal on the first node and connected between the first common node and a discharging voltage line;

a second switching element turned-on/off by a signal on the first common node and connected between the first node and the discharging voltage line;

a second active switching element connected between a second AC voltage line and a second common node;

a third switching element turned-on/off by the signal on the first node and connected between the second common node and the discharging voltage line;

a fourth switching element turned-on/off by a signal on the second common node and connected between the first node and the discharging voltage line;

a third active switching element connected between the first AC voltage line and a third common node;

a fifth switching element turned-on/off by the signal on the second node and connected between the third common node and a discharging voltage line;

a sixth switching element turned-on/off by a signal on the third common node and connected between the second node and the discharging voltage line;

a fourth active switching element connected between the second AC voltage line and a fourth common node;

a seventh switching element turned-on/off by the signal on the second node and connected between the fourth common node and the discharging voltage line; and

an eighth switching element turned-on/off by a signal on the fourth common node and connected between the second node and the discharging voltage line.

22. The dual shift register claimed as claim 21, wherein gate and drain terminals of the first active switching element are connected with the first AC voltage line.

23. The dual shift register claimed as claim 21, wherein gate and drain terminals of the second active switching element are connected with the second AC voltage line.

24. The dual shift register claimed as claim 21, wherein gate and drain terminals of the third active switching element are connected with the first AC voltage line.

25. The dual shift register claimed as claim 21, wherein gate and drain terminals of the fourth active switching element are connected with the second AC voltage line.