METHODS OF FORMING NONVOLATILE MEMORY DEVICES HAVING ELECTROMAGNETICALLY SHIELDING SOURCE PLATES

• US 20120115294A1
• Filed: 01/12/2012
• Published: 05/10/2012
• Est. Priority Date: 06/03/2008
• Status: Active Grant

• Current Assignee: Unification Technologies LLC (Acacia Research Corporation)
• Original Assignee: Jong Won Kim, Woon-Kyung Lee
• Inventors: Kim, Jong-Won, Lee, Woon-Kyung
• Granted Patent: US 8,404,578 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

Claims

1. A method of forming a non-volatile memory device, comprising:

forming a first interlayer insulating layer on a memory array having a plurality of strings of non-volatile memory cells therein at side-by-side locations in a semiconductor substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors, a plurality of rows of non-volatile memory cells and a row of string select transistors;

patterning the first interlayer insulating layer to define at least one source region contact opening therein that exposes at least one source region of a ground select transistor, and also define a plurality of drain region contact openings therein that expose respective drain regions of corresponding string select transistors;

depositing an electrically conductive layer that extends onto the first interlayer insulating layer and into the at least one source region contact opening and the plurality of drain region contact openings;

patterning the deposited electrically conductive layer into a source plate that covers the plurality of strings of non-volatile memory cells and into a plurality of bit line contact plugs;

forming a second interlayer insulating layer on the source plate and the plurality of bit line contact plugs;

patterning the second interlayer insulating layer to define a plurality of bit line contact openings therein that expose corresponding ones of the plurality of bit line contact plugs; and

forming a plurality of bit lines that extend on the second interlayer insulating layer and into the plurality of bit line contact openings.

2. The method of claim 1, wherein said patterning the second interlayer insulating layer comprises patterning the second interlayer insulating layer to define a source plate contact opening therein;

and wherein said forming a plurality of bit lines comprises forming a source line that extends on the second interlayer insulating layer and into the source plate contact opening.

3. The method of claim 1, wherein the source plate has a width greater than a spacing between a pair of adjacent strings in the plurality of strings of non-volatile memory cells and a length greater than a distance between a word line associated with an uppermost non-volatile memory cell in a first one of the plurality of strings of non-volatile memory cells and a word line associated with a lowermost non-volatile memory cell in the first one of the plurality of strings of non-volatile memory cells.

4. A method of fabricating a semiconductor device, comprising:

forming memory cell transistors on a semiconductor substrate, the memory cell transistors being disposed between source and drain electrodes to constitute a cell string;

forming a source plate over the memory cell transistors, the source plate being connected to the source electrodes and having an opening over at least one of the drain electrodes; and

forming a bitline structure over the source plate, the bitline structure being connected to the drain electrodes,

wherein the source plate is formed to veil the memory cell transistors thereunder.

5. The method as set forth in claim 4, wherein forming the memory cell transistors comprises:

forming isolation patterns on the semiconductor substrate to define active regions;

forming gate electrodes to cross over the active region; and

forming impurity regions between the gate electrodes,

wherein the gate electrodes include a ground selection line adjacent to the source electrode, a string selection line adjacent to the drain electrode, wordlines disposed between the ground and string selection lines.

6. The method as set forth in claim 5, wherein forming the source plate comprises:

forming an interlayer dielectric on the resultant structure where the gate electrode are formed;

forming a trench by patterning the interlayer dielectric to expose the source electrodes at one side of the ground selection line;

forming a common source line in the trench to be connected to the source electrodes;

forming a source electrode layer on the entire surface of the resultant structure, where the common source line is formed, to be connected the common source line; and

forming an opening by patterning the source electrode layer to expose the interlayer dielectric over the drain electrode.

7. The method as set forth in claim 5, wherein forming the source plate comprises:

forming an interlayer dielectric on the resultant structure where the gate electrodes are formed;

forming a trench by patterning the interlayer dielectric to expose the source electrodes at one side of the ground selection line;

forming a source electrode layer to fill the trench and cover the interlayer dielectric; and

forming the opening by patterning the source electrode layer to expose the interlayer dielectric over the drain electrode.

8. The method as set forth in claim 5, wherein the gate electrodes include a charge trapping layer or a floating gate electrode.

9. The method as set forth in claim 5, wherein a sidewall of the opening is formed over the string selection line.

10. The method as set forth in claim 4, further comprising:

forming a diffusion barrier layer in the opening before formation of the bitline structure.

11. The method as set forth in claim 4, further comprising:

forming pads connected to the drain electrodes, the pads being formed using a step of forming the source plate.

12. The method as set forth in claim 4, wherein forming the bitline structure comprises:

forming bitline plugs to be electrically connected to the drain electrodes through the opening; and

forming bitlines to be connected to the bitline plugs, respectively.

13. A method of fabricating a semiconductor device, comprising:

forming a memory array comprising a plurality of strings of non-volatile memory cells located at side-by-side locations in a substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors;

forming a plurality of bit lines electrically coupled to respective ones of the plurality of strings of non-volatile memory cells; and

forming a source plate electrically coupled to source regions of the row of ground select transistors via a common source line which is formed a linear shape, and said source plate extending in two-dimensions over a plurality of word lines associated with each of the plurality of strings of non-volatile memory cells.

14. The method of claim 13, wherein said source plate extends as an uninterrupted layer across a plurality of rows of the plurality of strings of non-volatile memory cells.

15. The method of claim 14, wherein said source plate extends between said plurality of bit lines and said plurality of strings of non-volatile memory cells.

16. The method of claim 15, wherein each of the plurality of strings of non-volatile memory cells comprises a string select transistor having a drain region in the substrate;

and wherein each of said plurality of bit lines is electrically coupled to a corresponding drain region of a string select transistor.

17. The method of claim 13, wherein each of the plurality of strings of non-volatile memory cells comprises a string select transistor having a drain region in the substrate;

and wherein each of said plurality of bit lines is electrically coupled to a corresponding drain region of a string select transistor.

18. The method of claim 16, further comprising a source line electrically coupled by a source line plug to said source plate;

and wherein said source line is coplanar with said plurality of bit lines.

19. The method of claim 13, wherein each of the plurality of strings of non-volatile memory cells comprises a string select transistor having a drain region in the substrate;

and wherein each of said plurality of bit lines is electrically coupled by a bit line plug to a corresponding drain region of a string select transistor.

20. The method of claim 19, further comprising a diffusion barrier layer surrounding each of a plurality of the bit line plugs;

and wherein the diffusion barrier layer is coplanar with said source plate.

21. The method of claim 20, wherein the diffusion barrier layer comprises an electrically insulating material selected from a group consisting of silicon nitride and silicon oxynitride.