METHOD OF FABRICATING DAMASCENE STRUCTURES

• US 20120115303A1
• Filed: 01/20/2012
• Published: 05/10/2012
• Est. Priority Date: 11/08/2010
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Lindgren, Peter J., Stamper, Anthony K.
• Granted Patent: US 8,293,638 B2
• Time in Patent Office: Days
• US Class Current: 438/399
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 2221/1021 Pre-forming the dual damascene structure in a resist layer
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

Claims

1. A method, comprising:

(a) forming a wire in a first dielectric layer on a substrate;

(b) forming a dielectric barrier layer over said wire and said first dielectric layer;

(c) forming a second dielectric layer over said barrier layer;

after (c), (d) forming a first patterned photoresist layer over said second dielectric layer;

after (d), (e) performing a first reactive ion etch to etch a first trench in said second dielectric layer;

after (e), (f) removing said first patterned photoresist layer using a plasma;

after (f), (g) forming a second patterned photoresist layer over said second dielectric layer;

after (g), (h) performing a second reactive ion etch to etch a second trench in said second dielectric layer, said first and second trenches open to each other, regions of said barrier layer exposed by said first and second trenches;

after (h), (i) performing a third reactive ion etch to remove said barrier layer exposed by said first and second trenches; and

after (i), (j) removing said second patterned photoresist layer using a reducing plasma or a non-oxidizing plasma.

2. The method of claim 1, wherein first reactive ion etch etches completely through said second dielectric layer and said second reactive ion etch etches part way through said second dielectric layer.

3. The method of claim 1, wherein first reactive ion etch etches part way through said second dielectric layer and said second reactive ion etch etches completely through said second dielectric layer.

4. The method of claim 1, further including:

filling said trench with an electrical conductor.

5. The method of claim 4, wherein said electrical conductor comprises copper or tungsten.

6. The method of claim 1, further including:

forming an electrically conductive liner on sidewalls and bottoms of said first and second trenches and on a top surface of said second dielectric layer;

filling remaining spaces in said first and second trenches with an electrically conductive core conductor; and

performing a chemical mechanical polish to form a wire by removing excess liner and core conductor so a top surface of said wire is coplanar with said top surface of said second dielectric layer.

7. The method of claim 1, wherein:

said first and second dielectric layers independently include a material selected from the group consisting of porous or nonporous silicon dioxide (SiO₂), porous or nonporous fluorinated SiO₂ (FSG), a low K (dielectric constant) material, porous or nonporous hydrogen silsesquioxane polymer (HSQ), porous or nonporous methyl silsesquioxane polymer (MSQ), porous or nonporous organosilicate glass (methyl doped silica or SiO_x(CH₃)_y or SiC_xO_yH_y or SiCOH), and porous or nonporous polyphenylene oligomer; and

said barrier layer includes a material selected from the group consisting of silicon nitride (Si₃N₄), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), silicon carbon nitride (SiCN), and plasma-enhanced silicon nitride (PSiN_x).

8. The method of claim 1, wherein either a perimeter of said first trench is aligned within a perimeter of said second trench, or said perimeter of said second trench is aligned within said perimeter of said first trench.

9. A method, comprising:

(a) forming a first wire in a first dielectric layer on a substrate and forming a barrier layer over a first wire and first dielectric layer;

after (a), (b) forming a second dielectric layer over said barrier layer;

after (b), (c) forming a capacitor on said first barrier layer, said capacitor comprising an insulator between first and second metal plates, an extending region of said first plate extending past said insulator and said second plate;

after (c), (d) forming a capping layer on said capacitor;

after (d), (e) forming a second dielectric layer on said barrier layer and said capping layer;

after (e), (f) forming a first patterned photoresist layer over said second dielectric layer;

after (g), (h) performing a first reactive ion etch to etch a first trench through said second dielectric layer to said barrier layer over said first wire, a second trench through said second dielectric layer to said capping layer over said extending region of said first plate, and a third trench through said second dielectric layer to said capping layer over said second plate;

after (h), (i) removing said first patterned photoresist layer using a plasma;

after (i), (j) forming a second patterned photoresist layer over said second dielectric layer;

after (j), (k) performing a second reactive ion etch to etch a fourth trench part way through said second dielectric layer over said first and second trenches and to etch a fifth trench part way through said second dielectric layer over said third trench;

after (k), (l) performing a third reactive ion etch to extend said first trench though said barrier layer and to extend said second and third trenches through said capping layer; and

after (l), (m) removing said second patterned photoresist layer using a reducing plasma or a non-oxidizing plasma.

10. The method of claim 9, further including:

filling said first, second, third, forth and fifth trenches with an electrical conductor.

11. The method of claim 10, wherein said electrical conductor comprises copper.

12. The method of claim 9, further including:

forming an electrically conductive liner on sidewalls and bottoms of said first, second, third, fourth and fifth trenches and on a top surface of said second dielectric layer;

filling remaining space in said first, second, third, fourth and fifth trenches with an electrically conductive core conductor; and

performing a chemical mechanical polish to form a second wire connecting said first wire and said extending region of said first plate and a third wire contacting said second plate by removing excess liner and core conductor so top surfaces of said second and third wires are coplanar with said top surface of said second dielectric layer.

13. The method of claim 9, wherein:

said first and second dielectric layers independently include a material selected from the group consisting of porous or nonporous silicon dioxide (SiO₂), porous or nonporous fluorinated SiO₂ (FSG), a low K (dielectric constant) material, porous or nonporous hydrogen silsesquioxane polymer (HSQ), porous or nonporous methyl silsesquioxane polymer (MSQ), porous or nonporous organosilicate glass (methyl doped silica or SiO_x(CH₃)_y or SiC_xO_yH_y or SiCOH), and porous or nonporous polyphenylene oligomer; and

said barrier layer includes a material selected from the group consisting of silicon nitride (Si₃N₄), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), silicon carbon nitride (SiCN), and plasma-enhanced silicon nitride (PSiN_x).

14. The method of claim 9, further including:

between (e) and (d) forming an etch stop layer on said barrier layer and said capping layer; and

wherein said first reactive ion etch includes a first step etching through regions of said etch stop layer exposed in bottoms of said first, second and third trenches and a second step etching through said barrier layer and through said capping layer exposed by said etching through said etch stop layer.