CONFIGURABLE 2-WIRE/3-WIRE SERIAL COMMUNICATIONS INTERFACE

• US 20120117284A1
• Filed: 11/04/2011
• Published: 05/10/2012
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Southcombe, William David, Jones, David E., Levesque, Chris, Yoder, Scott, Stockert, Terry J., Ngo, Christopher Truong
• Granted Patent: US 8,983,410 B2
• Time in Patent Office: Days
• US Class Current: 710/105
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.

Claims

1. Circuitry comprising:

sequence processing circuitry adapted to initiate processing of a received sequence based on a start-of-sequence (SOS) detection signal, such that the received sequence is associated with one of a plurality of serial communications protocols; and

SOS detection circuitry adapted to;

when coupled to a 2-wire serial communications bus, detect an SOS based on a serial data signal and a serial clock signal;

when coupled to a 3-wire serial communications bus, detect an SOS based on a chip select (CS) signal; and

in response to detecting the SOS, provide the SOS detection signal to the sequence processing circuitry.

2. The circuitry of claim 1 wherein:

when coupled to the 2-wire serial communications bus, the SOS detection circuitry is further adapted to receive the serial data signal and the serial clock signal via the 2-wire serial communications bus;

when coupled to the 3-wire serial communications bus, the SOS detection circuitry is further adapted to receive the serial data signal, the serial clock signal, and the CS signal via the 3-wire serial communications bus; and

the sequence processing circuitry is further adapted to initiate the processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS.

3. The circuitry of claim 1 wherein:

the SOS detection circuitry has a CS input;

the SOS detection circuitry comprises a CS resistive element coupled to the CS input; and

when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the CS input is adapted to receive the CS signal.

4. The circuitry of claim 3 wherein the CS resistive element is coupled between the CS input and a ground.

5. The circuitry of claim 1 wherein the SOS detection circuitry is further adapted to detect the SOS based on a pulse of the serial data signal, such that during the pulse of the serial data signal, the serial clock signal does not transition.

6. The circuitry of claim 1 wherein when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the SOS detection circuitry is further adapted to:

receive the serial data signal and receive the serial clock signal via the 3-wire serial communications bus; and

detect an SOS based on the serial data signal and the serial clock signal.

7. The circuitry of claim 1 wherein the SOS detection circuitry and the sequence processing circuitry provide a first configurable 2-wire/3-wire serial communications interface (C23SCI).

8. The circuitry of claim 7 wherein the sequence processing circuitry is further adapted to receive a protocol configuration signal, such that the sequence processing circuitry is inhibited from processing a received sequence associated with at least one of the plurality of serial communications protocols based on the protocol configuration signal.

9. The circuitry of claim 8 further comprising a power amplifier (PA)-digital communications interface (DCI) and PA control circuitry, which is adapted to provide the protocol configuration signal, wherein the first C23SCI is the PA-DCI.

10. The circuitry of claim 8 further comprising a direct current (DC)-DC converter digital communications interface (DCI) and DC-DC control circuitry, which is adapted to provide the protocol configuration signal, wherein the first C23SCI is the DC-DC converter DCI.

11. The circuitry of claim 7 wherein the sequence processing circuitry is further adapted to:

receive a sequence abort signal, such that the sequence processing circuitry is further adapted to abort processing of the received sequence based on the sequence abort signal; and

when the SOS detection circuitry is coupled to the 3-wire serial communications bus, the sequence abort signal is based on the CS signal.

12. The circuitry of claim 11 wherein the sequence abort signal is further based on a sequence abort enable signal.

13. The circuitry of claim 11 further comprising a power amplifier (PA)-digital communications interface (DCI) and PA control circuitry, which is adapted to provide the sequence abort signal, wherein the first C23SCI is the PA-DCI.

14. The circuitry of claim 11 further comprising a direct current (DC)-DC converter digital communications interface (DCI) and DC-DC control circuitry, which is adapted to provide the sequence abort signal, wherein the first C23SCI is the DC-DC converter DCI.

15. The circuitry of claim 7 wherein the first C23SCI is a mobile industry processor interface.

16. The circuitry of claim 15 wherein the first C23SCI is a radio frequency (RF) front-end (FE) interface.

17. The circuitry of claim 7 wherein the first C23SCI is a slave device.

18. The circuitry of claim 7 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising a first final stage having a first final bias input, such that bias of the first final stage is via the first final bias input;

PA control circuitry;

a PA-digital communications interface (DCI) coupled between a digital communications bus and the PA control circuitry; and

a final stage current digital-to-analog converter (IDAC) coupled between the PA control circuitry and the first final bias input.

19. The circuitry of claim 18 wherein the first C23SCI is the PA-DCI.

20. The circuitry of claim 7 further comprising:

a first radio frequency (RF) power amplifier (PA) having a first final stage and adapted to;

receive and amplify a first RF input signal to provide a first RF output signal; and

receive a first final bias signal to bias the first final stage;

PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal; and

a direct current (DC)-DC converter adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

21. The circuitry of claim 7 further comprising:

a direct current (DC)-DC converter comprising;

a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry.

22. The circuitry of claim 21 further comprising a second C23SCI wherein:

the RF PA circuitry comprises a PA-digital communications interface (DCI) coupled to a digital communications bus, such that the first C23SCI is the PA-DCI; and

the DC-DC converter further comprises a DC-DC converter DCI coupled to the digital communications bus, such that the second C23SCI is the DC-DC converter DCI.

23. The circuitry of claim 7 further comprising:

multi-mode multi-band radio frequency (RF) power amplification circuitry having at least a first RF input and a plurality of RF outputs, such that;

configuration of the multi-mode multi-band RF power amplification circuitry associates one of the at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with configuration information;

power amplifier (PA) control circuitry coupled between the multi-mode multi-band RF power amplification circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least a first look-up table (LUT), which provides the configuration information defined by at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus.

24. The circuitry of claim 23 wherein the first C23SCI is the PA-DCI.

25. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

a second RF PA comprising a second quadrature PA path coupled to the antenna port,

wherein the antenna port is configured to be coupled to an antenna.

26. The circuitry of claim 1 further comprising:

a first multi-mode multi-band quadrature radio frequency (RF) power amplifier (PA) coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

27. A method comprising:

providing sequence processing circuitry and start-of-sequence (SOS) detection circuitry;

initiating processing of a received sequence based on an SOS detection signal, such that the received sequence is associated with one of a plurality of serial communications protocols;

when coupled to a 2-wire serial communications bus, detecting an SOS based on a serial data signal and a serial clock signal;

when coupled to a 3-wire serial communications bus, detecting an SOS based on a chip select (CS) signal;

in response to detecting the SOS, providing the SOS detection signal.