METADATA STORAGE ASSOCIATED WITH FLASH TRANSLATION LAYER

• US 20120117303A1
• Filed: 11/04/2010
• Published: 05/10/2012
• Est. Priority Date: 11/04/2010
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Numonyx BV (Micron Technology, Inc.)
• Inventors: Carannante, Procolo, Di Sena, Angelo, Salvati, Fabio, Ferrari, Giuseppe, Sorgente, Anna
• Application Number:
  US12/939,953
• Publication Number:
  US 20120117303A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Subject matter disclosed herein relates to storing information via a NAND flash translation layer.

Claims

1. A method comprising:

receiving a write request via a flash translation layer to store information in a NAND or NAND-based memory array;

determining metadata of said information;

writing said information in said NAND or NAND-based memory array; and

writing said metadata in a second memory, said second memory comprising a type of nonvolatile memory other than that of said NAND or NAND-based memory array.

2. The method of claim 1, further comprising:

determining an error correction code (ECC) of said information; and

writing said ECC in said NAND or NAND-based memory array.

3. The method of claim 1, further comprising:

writing bad block information in said NAND or NAND-based memory array.

4. The method of claim 1, wherein said writing said information in said NAND or NAND-based memory array and said writing said metadata in said second memory are performed concurrently with one another.

5. The method of claim 1, wherein said second memory comprises phase change memory (PCM).

6. The method of claim 1, wherein said metadata comprises sector numbers and/or virtual block addresses of said NAND or NAND-based memory array.

7. The method of claim 1, wherein said NAND or NAND-based memory array comprises a multi-level NAND or NAND-based memory array.

8. The method of claim 5, moving markers and/or commits to said PCM to provide power loss recovery on a NOP-1 device.

9. A memory device comprising:

a NAND or NAND-based memory array to store information associated with a write request received via a flash translation layer; and

a second memory comprising a type of nonvolatile memory other than that of said NAND or NAND-based memory array to store metadata of said information, wherein said flash translation layer is adapted to write said information in said NAND or NAND-based memory array and to write said metadata in said second memory in a parallel process.

10. The memory device of claim 9, wherein said flash translation layer is further adapted to write an error correction code (ECC) of said information in said NAND or NAND-based memory array.

11. The memory device of claim 9, wherein said flash translation layer is further adapted to write bad block information in said NAND or NAND-based memory array.

12. The memory device of claim 9, wherein said second memory comprises phase change memory (PCM).

13. The memory device of claim 12, wherein said flash translation layer comprises a NAND driver and a PCM driver.

14. The memory device of claim 9, wherein said flash translation layer comprises hardware and/or software to manage bad blocks of said NAND or NAND-based memory array and to manage wear leveling of said NAND or NAND-based memory array.

15. The memory device of claim 9, wherein said metadata comprises sector numbers and/or virtual block addresses of said NAND or NAND-based memory array.

16. A system comprising:

a memory device comprising at least one array of NAND memory cells, said memory device further comprising a flash translation layer to;

receive a write request to store information in said array of NAND memory cells;

determine metadata of said information;

write said information in said array of NAND memory cells; and

write said metadata in a second memory comprising a type of nonvolatile memory other than that of said array of NAND memory cells; and

a processor to host one or more applications and to initiate said write request to said flash translation layer to provide access to said array of NAND memory cells in said memory device.

17. The system of claim 16, wherein said flash translation layer is adapted to:

determine an error correction code (ECC) of said information; and

write said ECC in said array of NAND memory cells.

18. The system of claim 16, wherein said flash translation layer is adapted to:

write bad block information in said array of NAND memory cells.

19. The system of claim 16, wherein said writing said information in said array of NAND memory cells and said writing said metadata in said second memory are performed concurrently with one another.

20. The system of claim 16, wherein said metadata comprises sector numbers and/or virtual block addresses of said array of NAND memory cells.