SENSE OPERATION FLAGS IN A MEMORY DEVICE

• US 20120117306A1
• Filed: 11/09/2010
• Published: 05/10/2012
• Est. Priority Date: 11/09/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahmed, Shafqat, Hasnat, Khaled, Kalavade, Pranav, Parat, Krishna, Yip, Aaron, Helm, Mark A., Bicksler, Andrew
• Granted Patent: US 9,135,998 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/224 Disk storage
• CPC Class Codes: G06F 2212/461 Sector or disk block
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Claims

1. A method for reading a memory device having a plurality of pages of memory cells, the method comprising:

reading a first page of memory cells and flag data from a set of flag cells wherein the flag data indicates whether an adjacent page of memory cells to the first page is programmed; and

determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage.

2. The method of claim 1 wherein reading the first page of memory cells and the flag data is performed substantially simultaneously with one read operation.

4. The method of claim 1 wherein the first page of memory cells is an even page, the adjacent page is an odd page, and the flag data indicates whether the odd page is programmed.

5. A memory device comprising:

a main memory cell array;

an flag memory cell array comprising first and second flag memory cell array data lines and coupled to the main memory array, the flag memory cell array configured to store indications that memory cells of an adjacent page are programmed;

a sense amplifier coupled to both the main memory cell array and the flag memory cell array and configured to store data for the main memory cell array; and

multiplexing circuitry that couples the main memory cell array and the flag memory cell array to the sense amplifier wherein the multiplexing circuitry is configured such that the first flag memory cell array data lines are fixably coupled to the sense amplifier.

6. The memory device of claim 5 wherein the flag memory cell array is part of the main memory cell array.

7. The memory device of claim 5 and further comprising a standard flag memory cell array coupled to the main memory cell array.

8. The memory device of claim 5 wherein the sense amplifier is configured to store data from the flag memory cell array.

9. The memory device of claim 5 wherein the second flag memory cell array data line is not coupled to the sense amplifier.

10. The memory device of claim 5 wherein the main memory cell array comprises a NAND architecture.

11. A memory device comprising:

a memory cell array comprising a main memory cell array and a flag memory cell array; and

a data cache coupled to the memory cell array, the data cache configured to store data to be programmed to and read from the main memory cell array and the flag memory cell array

wherein a first main memory cell data line and a second main memory cell data line are configured to be selectively coupled to the data cache, wherein a first flag cell memory array data line is fixably coupled to the data cache, and wherein a second flag cell memory array data line is not coupled to the data cache.

12. The memory device of claim 11 wherein the data cache comprises a plurality of data caches.

13. The memory device of claim 12 wherein the plurality of data caches comprise a temporary data cache, a first dynamic data cache, a second dynamic data cache, a primary data cache, and a secondary data cache.

14. The memory device of claim 12 wherein the data cache further comprises a precharge circuit that is configured to precharge the data lines.

15. The memory device of claim 13 wherein the secondary data cache is coupled to an input/output connection of the memory device.

16. The memory device of claim 11 wherein the first data lines comprise odd bit lines and the second data lines comprise even bit lines.

17. The memory device of claim 11 and further comprising multiplexing circuitry wherein the multiplexing circuitry comprises a respective select gate for each of the data lines, wherein the first flag cell memory array data lines bypass the select gate and connect directly to a sense amplifier and the second flag cell memory array data lines are disconnected across the select gate.

18. The memory device of claim 11 and further comprising multiplexing circuitry and wherein the multiplexing circuitry comprises a respective helper gate for each of the two data lines.

19. The memory device of claim 18 wherein a helper gate for the first flag cell memory array data line is disconnected from the first flag cell memory array data line and a helper gate for the second flag cell memory array data line is shorted to the second flag cell memory array data line.

20. A method for programming sense flags, the method comprising:

programming memory cells coupled to first data lines in a main memory array; and

programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed.

21. The method of claim 20 wherein programming the memory cells coupled to the first data lines further comprises loading user data into a dynamic data cache coupled to the first data lines prior to programming the memory cells coupled to the first data lines with the user data.

22. The method of claim 20 wherein programming memory cells coupled to the data lines in the flag memory array comprises programming data that includes both the flag data and other data associated with a particular page of data of the main memory array.

23. The method of claim 20 wherein the flag data comprises a plurality of bytes of data.

24. A method for sensing flags, the method comprising:

performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array; and

determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

25. The method of claim 24 and further comprising:

adjusting read gate voltages for a state of the memory cells coupled to the first data lines of the main memory array when the program indication indicates that the memory cells coupled to the second data lines of the main memory array are not programmed.

26. The method of claim 24 and further comprising:

determining states of the memory cells coupled to the first data lines of the main memory array without adjustment of read gate voltages when the program indication indicates that the memory cells coupled to the second data lines of the main memory array are programmed.

27. The method of claim 24 and further comprising:

performing a sense operation on a lower page of the memory cells coupled to the first data lines responsive to the program indication.

28. The method of claim 24 and further comprising:

adjusting read gate voltages for a state of the memory cells coupled to the first data lines of the main memory array when the program indication indicates that the memory cells coupled to the second data lines of the main memory array are programmed.

29. The method of claim 24 and further comprising:

determining states of the memory cells coupled to the first data lines of the main memory array without adjustment of read gate voltage when the program indication indicates that the memory cells coupled to the second data lines of the main memory array are not programmed.

30. A memory device comprising:

a memory array comprising a main memory cell array and a flag memory cell array;

a dynamic data cache coupled to the memory array and configured to store data read from the memory array and data to be programmed to the memory array;

multiplexing circuitry that couples the dynamic data cache to the memory array, the multiplexing circuitry configured to selectively multiplex first and second data lines of the main memory cell array to the dynamic data cache, disconnect the first data lines of the flag memory cell array from the dynamic data cache, and shorts second data lines of the flag memory cell array to the dynamic data cache; and

memory control circuitry configured to control operation of the memory device.

31. The memory device of claim 30 wherein the memory control circuitry is configured to simultaneously sense the first data lines of the main memory cell array and the second data lines of the flag memory cell array.