Hybrid Server with Heterogeneous Memory

• US 20120117312A1
• Filed: 12/27/2011
• Published: 05/10/2012
• Est. Priority Date: 06/24/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: CHAN, Yuk Lung, KRISHNAMURTHY, Rajaram B., PARRIS, Carl Joseph
• Granted Patent: US 9,069,977 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 16/172 Caching, prefetching or hoarding of files
• CPC Class Codes: G06F 16/182 Distributed file systems
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 2212/264 Remote server
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 41/5054 Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 67/568 Storing data temporarily at an intermediate stage, e.g. caching

Abstract

A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

Claims

1. A method, on a hybrid server system, for managing access to data stored thereon, the method comprising:

partitioning a memory system residing at a server into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems, wherein the set of accelerator systems are communicatively coupled to the server, and wherein the memory system comprises heterogeneous memory types;

identifying a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transforming the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

2. The method of claim 1, wherein the transforming is based on at least one of an operation associated with the data set and a type of processing core residing on the at least one accelerator system.

3. The method of claim 1, wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

4. The method of claim 1, further comprising:

determining that at least one accelerator system in the set of accelerator systems has completed processing data in a given portion of memory residing on the at least one accelerator system; and

accessing, in response to the determining, the given portion of memory.

5. The method of claim 1, further comprising:

determining that at least one data block within a fast memory of the memory system has been replaced;

moving the replaced data block from the fast memory to a slow memory of the memory system; and

moving the replaced data block from the slow memory to a disk storage.

6. The method of claim 1, further comprising:

communicating, by a first accelerator system in the set of accelerator systems, at least one data set residing within a flash memory module of the memory system to a second accelerator system in the set of accelerator systems over an input-output bus of the server, wherein the at least one flash memory module is communicatively coupled to the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

7. The method of claim 6, wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.

8. The method of claim 1, wherein each accelerator in the set of accelerators is assigned a private memory module within the memory system, and a public memory area within the memory system, wherein the public memory area is accessible by two or more accelerators in the set of accelerators.

9. A hybrid server system in an out-of-core processing environment comprising:

a server comprising

a memory system partitioned into a first set of memory managed by the server,

and a second set of memory managed by a set of accelerator systems, wherein the memory system comprises heterogeneous memory types, and

a data access manager communicatively coupled to the memory system; and

a set of accelerator systems communicatively coupled to the server, wherein each accelerator system in the set of accelerator systems comprises at least one processing core,

wherein the data access manager is configured to

identify a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transform the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

10. The hybrid server system of claim 9, wherein the transforming is based on at least one of an operation associated with the data set and a type of the at least one processing core of the at least one accelerator system.

11. The hybrid server system of claim 9, wherein partitioning the memory system comprises:

releasing the second set of memory to the set of accelerator systems.

12. The hybrid server system of claim 9, wherein at least one accelerator system in the set of accelerator systems comprises at least one gated memory, wherein the at least one accelerator system selectively allows the server to access the at least one gate memory.

13. The hybrid server system of claim 9, wherein the memory system comprises at least one flash memory module, and wherein the at least one flash memory module is communicatively coupled to an input-output bus of the server, wherein a first accelerator system in the set of accelerator systems communicates at least one data set residing within the flash memory to a second accelerator system in the set of accelerator systems over the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

14. The hybrid server system of claim 13, wherein the at least one flash memory module comprises a network link configured to at least one of send and receive messages from at least the set of accelerators.

15. The hybrid server system of claim 9, wherein each accelerator in the set of accelerators is assigned a private memory module within the memory system, and a public memory area within the memory system, wherein the public memory area is accessible by two or more accelerators in the set of accelerators.

16. A computer program product for managing data access in an out-of-core processing environment, the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

partitioning a memory system residing at a server into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems, wherein the set of accelerator systems are communicatively coupled to the server, and wherein the memory system comprises heterogeneous memory types;

identifying a data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems; and

transforming the data set from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.

17. The computer program product of claim 16, wherein the transforming is based on at least one of an operation associated with the data set and a type of processing core residing on the at least one accelerator system.

18. The computer program product of claim 16, wherein the method further comprises:

determining that at least one data block within a fast memory of the memory system has been replaced;

moving the replaced data block from the fast memory to a slow memory of the memory system; and

moving the replaced data block from the slow memory to a disk storage.

19. The computer program product of claim 16, wherein the method further comprises:

communicating, by a first accelerator system in the set of accelerator systems, at least one data set residing within a flash memory module of the memory system to a second accelerator system in the set of accelerator systems over an input-output bus of the server, wherein the at least one flash memory module is communicatively coupled to the input-output bus of the server, and wherein the first and second accelerator systems have direct access to the at least one flash memory module.

20. The computer program product of claim 16, wherein each accelerator in the set of accelerators is assigned a private memory module within the memory system, and a public memory area within the memory system, wherein the public memory area is accessible by two or more accelerators in the set of accelerators.