HETEROGENEOUS COMPUTING SYSTEM COMPRISING A SWITCH/NETWORK ADAPTER PORT INTERFACE UTILIZING LOAD-REDUCED DUAL IN-LINE MEMORY MODULES (LR-DIMMS) INCORPORATING ISOLATION MEMORY BUFFERS

• US 20120117318A1
• Filed: 11/01/2011
• Published: 05/10/2012
• Est. Priority Date: 11/05/2010
• Status: Abandoned Application

• Current Assignee: SRC Computers, LLC
• Original Assignee: SRC Computers, Inc.
• Inventors: Burton, Lee A., Seeman, Thomas R., Huppenthal, Jon M.
• Application Number:
  US13/286,996
• Publication Number:
  US 20120117318A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1663 Access to shared memory

Abstract

A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.

Claims

1. A computer system comprising:

at least one dense logic device;

an interleaved controller for coupling said at least one dense logic device to a control bus and a memory bus;

a plurality of memory slots coupled to said memory bus;

an adaptor port associated with at least two of said plurality of memory slots, each of said adapter ports including associated memory resources; and

a direct execution logic element coupled to at least one of said adapter ports, said memory resources being selectively accessible by said at least one dense logic device and said direct execution logic element.

2. The computer system of claim 1 wherein said plurality of memory slots comprise LR-DIMM memory module slots.

3. The computer system of claim 1 wherein said memory slots and said memory bus are coupled using one or more isolation memory buffers.

4. The computer system of claim 1 wherein said adapter port comprises a memory buffer.

5. A computer system comprising:

at least one dense logic device;

at least one controller for coupling said at least one dense logic device to a control bus and one or more memory buses;

a plurality of memory slots coupled to said memory bus;

one or more adaptor ports associated with at least one of said plurality of memory slots coupled to said one or more memory buses, each of said adapter ports including associated memory resources; and

a direct execution logic element coupled to at least one of said adapter ports, said memory resources being selectively accessible by said at least one dense logic device and said direct execution logic element.

6. The computer system of claim 5 wherein said one or more memory slots coupled to said one or more memory buses comprise at least one LR-DIMM memory module slots.

7. The computer system of claim 5 wherein said memory slots and said one or more memory buses are coupled using one or more isolation memory buffers.

8. The computer system of claim 5 wherein said at least one adapter port comprises a memory buffer.

9. A computer system comprising:

at least one dense logic device;

at least one controller for coupling said at least one dense logic device to a control bus and a memory bus supporting a single rank of memory;

an isolation memory buffer coupled to said memory bus;

a plurality of other memory buses connected to said isolation buffer;

one or more adaptor ports associated with at least one of said plurality of other memory buses, each of said adapter ports including associated memory resources; and

a direct execution logic element coupled to at least one of said adapter ports, said memory resources being selectively accessible by said at least one dense logic device and said direct execution logic element.

10. The computer system of claim 9 wherein said memory bus comprises a plurality of LR-DIMM memory module slots.

11. The computer system of claim 10 wherein said memory slots and said memory bus are coupled using one or more isolation memory buffers.

12. The computer system of claim 9 wherein said one or more adapter ports comprise a memory buffer.

13. A computer system comprising:

at least one dense logic device;

a controller for coupling said at least one dense logic device to a memory module bus;

a plurality of memory module slots coupled to said memory module bus;

an adapter port coupled to at least one of said plurality of memory module slots;

a direct execution logic element associated with said adapter port; and

an LR-DIMM memory module associated with another of said plurality of memory module slots.

14. The computer system of claim 13 further comprising:

a control bus coupled to said at least one dense logic device and said adapter port.

15. The computer system of claim 14 wherein said control bus indicates to said dense logic device r an arrival of data to said direct execution logic element on said memory module bus.

16. The computer system of claim 13 wherein said adapter port comprises a dual in-line memory module slot connector for retention within said at least one of said plurality of memory module slots.

17. The computer system of claim 13 further comprising:

an external device coupled to said direct execution logic element by a data connection.

18. The computer system of claim 17 wherein said external device comprises one of another computer system, switch or network.

19. The computer system of claim 17 wherein said direct execution logic element is operative to alter data received from said controller on said memory module bus prior to transmission on said data connection to said external device.

20. The computer system of claim 17 wherein said direct execution logic element is operative to alter data received on said data connection from said external device prior to transmission to said controller on said memory module bus.

21. The computer system of claim 17 wherein said direct execution logic element comprises:

at least one field programmable gate array configurable to perform an identified algorithm on an operand provided thereto on said memory module bus and said data connection.