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METHOD AND APPARATUS FOR DEFERRED SCHEDULING FOR JTAG SYSTEMS

  • US 20120117436A1
  • Filed: 12/28/2011
  • Published: 05/10/2012
  • Est. Priority Date: 03/04/2009
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a processing module configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP);

    a reordering buffer module configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test; and

    a vector transformation module configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

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