METHOD AND APPARATUS FOR DEFERRED SCHEDULING FOR JTAG SYSTEMS
First Claim
1. An apparatus, comprising:
- a processing module configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP);
a reordering buffer module configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test; and
a vector transformation module configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.
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Accused Products
Abstract
A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.
21 Citations
20 Claims
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1. An apparatus, comprising:
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a processing module configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP); a reordering buffer module configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test; and a vector transformation module configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A non-transitory computer-readable storage medium storing instruction which, when executed by a processor, cause the processor to perform a method, the method comprising:
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receiving a plurality of test operations associated with a plurality of segments of a unit under test; generating, from the test operations, input test data configured to be applied to the unit under test via a Test Access Port (TAP); buffering the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test; and applying a vector transformation for the input test vector. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method, comprising:
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receiving a plurality of test operations associated with a plurality of segments of a unit under test; generating, from the test operations, input test data configured to be applied to the unit under test via a Test Access Port (TAP); buffering the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test; and applying a vector transformation for the input test vector.
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Specification