3D SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SAME

• US 20120119287A1
• Filed: 11/16/2011
• Published: 05/17/2012
• Est. Priority Date: 11/17/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Sang-Yong, PARK, Jintaek, KIM, Hansoo, CHO, Wonseok, CHUNG, Juhyuck
• Granted Patent: US 8,564,050 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

Claims

1. A three dimensional (3D) semiconductor device comprising:

memory cells arranged in a plurality of layers vertically stacked on a substrate, wherein the memory cells are series connected by a vertical channel extending from a lower end proximate the substrate and coupled to a lower non-memory cell to an upper end coupled to an upper non-memory cell, wherein the plurality of layers collectively forms a stair-stepped structure and each one of the plurality of layers comprises a successively exposed end portion serving as a pad, and at least one of the upper non-memory cell and the lower non-memory cell comprises a plurality of vertically stacked non-memory cells connected as one conductive piece.

2. The 3D semiconductor device of claim 1, wherein the plurality of vertically stacked non-memory cells are connected by a conductor vertically extending from one pad of the plurality of layers including one of the plurality of vertically stacked non-memory cells.

3. The 3D semiconductor device of claim 2, wherein the conductor connects edges of respective gates of the plurality of vertically stacked non-memory cells.

4. The 3D semiconductor device of claim 3, further comprising:

a plurality of contacts making respective contact with the pad of one of the plurality of layers,

wherein one of the plurality of contacts vertically extends to contact and penetrate a pad of one of the plurality of layers including the upper non-memory cell.

5. A three dimensional (3D) semiconductor device comprising:

a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells; and

a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate, the gate stack comprising;

a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end,

a plurality of upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and

a plurality of intermediate layers respectively including a word line and coupled to a cell transistor, wherein the plurality of intermediate layers is disposed between the lower select line and the upper select line.

6. The 3D semiconductor device of claim 5, wherein the lower layer includes a lower pad exposed at one end by the plurality of intermediate layers,

the plurality of intermediate layers respectively includes a corresponding plurality of successively exposed intermediate pads, and

the plurality of upper layers respectively include one of a plurality of upper pads, wherein upper pads in the plurality of upper pads overlay one another.

7. The 3D semiconductor device of claim 6, wherein at least one of the lower pad and the pads of the plurality of upper pads is wider than any one of the intermediate pads.

8. The 3D semiconductor device of claim 5, wherein the plurality of upper layers comprises:

a first upper layer including a first conductive line coupled to a first upper non-memory transistor and having a first pad; and

a second upper layer disposed under the first upper layer and including a second conductive line coupled to a second upper non-memory transistor and having a second pad.

9. The 3D semiconductor device of claim 8, wherein the first and second pads are electrically connected and directly overlay one another.

10. The 3D semiconductor device of claim 9, further comprising a vertical conductor extending from the second upper layer to penetrate the first upper layer.

11. The 3D semiconductor device of claim 8, wherein the second pad is exposed by the first upper layer, and the semiconductor device further comprises:

a first conductor vertically extending from the first pad; and

a second conductor vertically extending from the second pad,

wherein the first and second conductive lines are connected via the first and second conductors.

12. The 3D semiconductor device of claim 6, wherein the lower pad is wider than the upper pads.

13. The 3D semiconductor of claim 5 wherein the lower select line is a ground select line and the upper select line is a string selection line.

14. A three dimensional (3D) semiconductor device comprising:

a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells; and

a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate, the gate stack comprising;

a plurality of lower layers respectively including conductive lines coupled to a lower non-memory transistor proximate the lower end and connected as a second conductive piece to form a lower select line,

a plurality of upper layers respectively including conductive lines coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and

a plurality of intermediate layers respectively including a word line coupled to a cell transistor, wherein the plurality of intermediate layer is disposed between the lower select line and the upper select line.

15. The 3D semiconductor device of claim 14, wherein the plurality of lower layers comprises:

a first lower layer including a first lower pad; and

a second lower layer including a second lower pad and disposed above the first lower layer.

16. The 3D semiconductor device of claim 15, wherein the first and second lower pads are electrically connected and overlay one another, and the semiconductor device further comprises a conductor vertically extending from the second lower pad.

17. The 3D semiconductor device of claim 15, wherein the first lower pad is exposed by the second lower layer, and the semiconductor device further comprises a first conductor vertically extending from the first lower pad, and a second conductor vertically extending from the second lower pad.

18. The 3D semiconductor device of claim 15, wherein at least one of the first and second lower pads is wider than any one of a plurality of intermediate pads respectively associated with the plurality of intermediate layers.

19. The 3D semiconductor of claim 14 wherein the lower select line is a ground select line and the upper select line is a string selection line.

20-30. -30. (canceled)