CONTROL CIRCUITRY IN A DC/DC CONVERTER FOR ZERO INDUCTOR CURRENT DETECTION

• US 20120119715A1
• Filed: 11/16/2010
• Published: 05/17/2012
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Loikkanen, Mikko T., Hauru, Juha O., Väänänen, Ari Kalevi
• Granted Patent: US 8,350,543 B2
• Time in Patent Office: Days
• US Class Current: 323/235
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A converter controller for discharge of a coil used in a DC/DC converter including a voltage detector connected to monitor a state of a diode connected between the coil and ground and an offset comparator, having an adjustable offset, for causing a coil discharge path to be interrupted. The comparator is provided with an initial high offset so that for at least a first converter switching period, the coil will have sufficient charge when the coil discharge path is interrupted to cause the diode to become forward biased as determined by the voltage detector. The offset is periodically reduced until the coil is sufficiently discharged so that the diode is not forward biased, with that value of offset being optimum and thus used in subsequent switching periods.

Claims

1. A converter controller for use in a DC/DC converter, with the converter including a coil having first and second ends, and a plurality of transistor switches connected to the coil and a diode having a cathode connected to the first end of the coil and an anode connected to a circuit reference, said controller comprising:

a switch controller configured, during a given switching period, to connect at least one of the transistor switches to provide a coil charging path and to connect at least one of the transistor switches to provide a coil discharging path, and wherein the at least one transistor for providing the coil discharging path has a turn OFF time controlled by a turn off signal;

a voltage detector configured to detect a polarity of a voltage across the diode and to produce in response thereto a detector output, including a first detector output when the polarity of the voltage tends to forward bias the body diode and a second detector output when the polarity of the voltage tends to reverse bias the diode;

an offset circuit configured to produce offset outputs, including a first offset output in response to receipt of the first detector output and a second offset output in response to receipt of the second detector output; and

an offset comparator configured to monitor a coil discharge current to produce the turn off signal, with the offset comparator having a comparator offset which can be adjusted so that a point at which an output of the offset comparator changes state can be altered in response to utilization the offset outputs, with the offset comparator forming part of a feedback path; and

wherein, in response to utilization of the first offset output by the offset comparator, the turn off signal operates to cause the at least one transistor for providing the coil discharge path to turn OFF at a time such that the voltage detector produces the first detector output and, in response to utilization of the second offset output by the offset comparator, the turn off signal operates to cause the at least one transistor for providing the coil discharge path to turn OFF at a time such that the voltage detector produces the second detector output, with the offset comparator utilizing the first offset output during one switching period and utilizing the second output offset output during a next switching period and during N number of subsequent switching periods that are consecutive with respect to the next switching period, where N is at least one.

2. The converter controller of claim 1 wherein the plurality of transistor switches of the converter includes a first transistor switch connected intermediate the first end of the coil and a converter input terminal and a second transistor switch connected intermediate the first end of the coil and the circuit reference, with the second transistor switch including the diode as a body diode and wherein the switch controller is further configured, during a given switching period, to turn the first transistor switch ON to form part at least part of the charging path and to turn the second transistor ON to form at least part of the discharging path and wherein the second transistor switch has the turn OFF time controlled by the turn off signal.

3. The converter controller of claim 1 wherein the plurality of transistor switches of the converter further includes a third transistor switch connected intermediate the second end of the coil and a converter output terminal and a fourth transistor switch connected intermediate the second end of the coil and the circuit reference, and wherein the switch controller is further configured, during a given switching period, to turn the third transistor ON to form at least part of the discharging path and to turn the fourth transistor switch ON to form at least part of the charging path.

4. The converter controller of claim 1 wherein the offset outputs are produced in a digital form and wherein the value of N is at least twenty.

5. The converter controller of claim 4 wherein the offset circuit includes an up/down counter, with an output of the up/down counter forming the offset outputs.

6. The converter controller of claim 5 wherein the up/down counter counts in response to a clock signal, with a counter up/down state being controlled by the detector output.

7. The converter controller of claim 6 wherein the switching periods and the clock have a same constant period.

8. The converter controller of claim 6 wherein the switching periods and the clock have a same variable period.

9. The converter controller of claim 2 wherein the offset circuit will operate to cause the offset comparator to turn the second transistor switch OFF at a relatively early time when the first detector output is present and at a relatively later time when the second detector output is present.

10. The converter controller of claim 1 wherein the offset comparator monitors the coil discharge current by sensing a voltage drop across a current sensing impedance disposed intermediate the second end of the coil and the converter output terminal.

11. The converter controller of claim 1 wherein the voltage detector includes a sample circuit which produces a first sampled voltage relating to the body diode anode voltage and a second sampled voltage relating to the body diode cathode voltage.

12. The converter controller of claim 11 where the voltage detector includes a comparator circuit configured to compare the first and second sampled voltages with one another to produce the voltage detector output.

13. The converter controller of claim 12 wherein the first and second sampled voltages are produced by sampling the respective body diode anode and cathode voltages after the second transistor switch is turned OFF.

14. The converter controller of claim 13 wherein the comparator circuit includes a strobe control input for initiating a comparison, with the strobe control input being triggered after the first and second sampled voltages are produced.

15. The converter controller of claim 14 wherein the comparator circuit includes a latching output which retains the detector outputs after the strobe control input has been triggered.

16. The converter controller of claim 1 wherein the comparator offset is provided, at least in part, by an offset voltage source having a magnitude which can be adjusted in response to the output offsets produced by the offset circuit.

17. The converter controller of claim 1 wherein the comparator offset is provided, at least in part, by a delay adjust circuit which alters a propagation delay of the offset comparator, wherein a magnitude of the propagation delay can be adjusted in response to the output offsets produced by the offset circuit.

18. A method of controlling discharge of a coil used in a DC/DC converter, with the converter including a diode having a cathode connected to one terminal of the coil, an anode connected to a circuit reference and a transistor switch that forms at least part of a discharge path for the coil, said method comprising:

(a) charging the coil during a switching period;

(b) commencing a discharge of the coil during the switching period through the transistor;

(c) turning OFF the transistor at a first point in time in the switching period while discharging the coil and then sampling a voltage across the diode to determine a polarity of the voltage;

(d) charging the coil during a subsequent switching period immediately following the previous switching period;

(e) commencing a discharge of the coil during the subsequent switching period through the transistor;

(f) turning OFF the transistor at a second point in time in the subsequent switching period while discharging the coil, with the second point in time being later in the subsequent switching period than the first point in time in the previous switching period and then sampling the voltage across the diode to determine the polarity of the voltage;

wherein the first point of time is sufficiently early in the switching period so that the a remaining charge on the coil will produce a voltage having a polarity which will tend to forward bias the diode, and wherein steps (d) through (f) are repeated for subsequent switching periods until the polarity of the voltage reverses in which case the point in time of transistor turn OFF during that switching period of polarity reversal is used as a transistor turn OFF time during a next N number of consecutive of switching periods where N is greater than one.

19. The method of claim 18 wherein changes in transistor turn off time from one switching period to a next switching period are controlled by a digital offset word.

20. The method of claim 19 where the digital offset word is maintained fixed in value for the N number of switching periods, where N is at least twenty, and then the digital offset word is either increased or decreased in value depending upon the polarity of the voltage across the diode.