Orthogonal Basis Function Set for Digital Predistorter

• US 20120119831A1
• Filed: 11/16/2010
• Published: 05/17/2012
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Bai, Chunlong
• Granted Patent: US 8,368,466 B2
• Time in Patent Office: Days
• US Class Current: 330/149
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3252 using multiple parallel paths between input and output H03F1/3258, H03F1/3282, H03F1/3294 take precedence
• CPC Class Codes: H03F 1/3258 based on polynomial terms
• CPC Class Codes: H03F 2201/3209 the amplifier comprising means for compensating memory effects
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/24 of transmitter output stages

Abstract

A predistorter applies a distortion function to an input signal to predistort the input signal. The output of the distortion function is modeled as the sum of the output signals from the orthogonal basis functions weighted by corresponding weighting coefficients. Techniques are described for orthogonalizing the basis function output signals depending on the distribution of the input signal.

Claims

1. A method of compensating for distortion of an input signal by an electronic device that operates on the input signal to produce an output signal, said method comprising:

computing a set of model coefficients for a two-dimensional lattice prediction model of a basis function set from a set of input signal samples over a predetermined sampling interval, wherein the lattice prediction model represents basis functions in a predistorter basis function set as different combinations of power basis functions;

determining, from said set of model coefficients, a corresponding set of predistorter connection coefficients for combining power basis function output signals from the power basis functions to generate basis function output signals;

computing a set of power basis function output signals from an input signal and the set of power basis functions;

applying the set of predistorter connection coefficients to the power basis function output signals to produce a set of basis function output signals; and

combining the basis function output signals to produce a predistorted input signal from the input signal.

2. The method of claim 1 wherein computing a set of model coefficients from a set of input signal samples comprises:

computing, for each input signal sample, a model set of power basis function output signals;

normalizing the model set of power basis function output signals by multiplying said power basis function output signals by corresponding normalization factors; and

computing the set of model coefficients from the normalized model set of power basis function output signals.

3. The method of claim 2 wherein computing the set of model coefficients from the normalized model set of power basis function output signals comprises:

computing forward and backward prediction errors for model connecting nodes in said lattice prediction model from the normalized model set of power basis function output signals; and

normalizing the forward and backward prediction errors so that the forward and backward prediction errors have a predetermined variance; and

computing the model coefficients for the model connecting nodes from the normalized forward and backward prediction errors.

4. The method of claim 1 wherein the predistorter applies the lattice prediction model to produce the basis function output signals and wherein the predistorter connection coefficients comprise the model coefficients for the lattice prediction model.

5. The method of claim 1 wherein the predistorter applies a linear model to produce the basis function output signals from the predistorter input signal and wherein the predistorter connection coefficients are computed from the model coefficients.

6. The method of claim 5 wherein the predistorter connection coefficients are computed as products of the models coefficients multiplied by corresponding normalization factors for the predistorter connecting nodes.

7. The method of claim 1 wherein computing a set of power basis function output signals comprises computing, for each of a plurality of sampling time instances, a set of basis function output signals from a single input signal sample and the set of power basis functions.

8. A circuit for compensating an input signal for distortion introduced by an electronic device operating on an input signal to produce an output signal, said circuit comprising:

a basis function modeling circuit configured to;

compute a set of model coefficients for a two-dimensional lattice prediction model of a basis function set from a set of input signal samples over a predetermined sampling interval, wherein the lattice prediction model represents basis functions in a predistorter basis function set as different combinations of power basis functions in a set of power basis functions;

determine, from said set of model coefficients, a corresponding set of predistorter connection coefficients for combining power basis function output signals from the power basis functions to generate basis function output signals;

a predistorter configured to;

compute a set of power basis function output signals from an input signal and the set of power basis functions;

apply the set of predistorter connection coefficients to the power basis function output signals to produce a set of basis function output signals; and

combine the basis function output signals to produce a predistorted input signal from the input signal.

9. The circuit of claim 8 wherein the basis function modeling circuit is configured to compute a set of model coefficients by:

computing, for each input signal sample, a model set of power basis function output signals;

normalizing the model set power basis function output signals by multiplying said power basis function output signals by corresponding normalization factors;

computing the set of model coefficients from the normalized model set of power basis function output signals.

10. The circuit of claim 9 wherein the basis function modeling circuit is configured to compute the set of model coefficients from the normalized model set of power basis function output signals by:

computing forward and backward prediction errors for model connecting nodes in said lattice prediction model from the normalized model set of power basis function output signals; and

normalizing the forward and backward prediction errors so that the forward and backward prediction errors have a predetermined variance; and

computing the model coefficients for the model connecting nodes from the normalized forward and backward prediction errors.

11. The circuit of claim 8 wherein the predistorter is configured to apply the lattice prediction model to produce the basis function output signals and wherein the predistorter connection coefficients comprise for the model coefficients for the lattice prediction model.

12. The circuit of claim 8 wherein the predistorter is configured to apply a linear model to produce the basis function output signals from the predistorter input signal and wherein the predistorter connection coefficients are computed from the model coefficients.

13. The circuit of claim 12 wherein the predistorter is configured to compute the predistorter connection coefficients are computed as a product of the model coefficients by respective normalization factors for the predistorter connecting nodes.

14. The circuit of claim 8 wherein the predistorter is configured to compute, for each of a plurality of sampling time instances, a set of basis function output signals from a single input signal sample and the set of power basis functions.