Level Shifter, System-on-Chip Including the Same, and Multimedia Device Including the Same

• US 20120120082A1
• Filed: 11/09/2011
• Published: 05/17/2012
• Est. Priority Date: 11/12/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ku, Jachun, Lim, Kyoungmook
• Granted Patent: US 8,970,454 B2
• Time in Patent Office: Days
• US Class Current: 345/520
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.

Claims

1. A level shifter, comprising:

an input node;

first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node; and

an output node configured to output the output clock,

wherein the first and second voltage shifter circuits have a same structure and are connected in parallel between the input node and an output node.

2. The level shifter as claimed in claim 1, wherein the first voltage shifter circuit includes at least two inverters operating at the second voltage domain.

3. The level shifter as claimed in claim 1, wherein the second voltage shifter circuit includes at least one inverter operating at the first voltage domain and at least one inverter operating at the second voltage domain.

4. The level shifter as claimed in claim 3, wherein the at least one inverter operating at the second voltage domain is configured to receive an output of the at least one inverter operating at the first voltage domain.

5. The level shifter as claimed in claim 1, wherein:

the first voltage shifter circuit includes a first inverter configured to output a second voltage or a ground voltage according to a voltage of the input node, and a second inverter configured to output the second voltage or the ground voltage to the output node according to an output of the first inverter, and

the second voltage shifter circuit includes a third inverter configured to output the first voltage or the ground voltage according to a voltage of the input node, and a fourth inverter configured to output the second voltage or the ground voltage to the output node according to an output of the third inverter.

6. The level shifter as claimed in claim 5, wherein the first to fourth inverters are CMOS inverters.

7. A system-on-chip, comprising:

a phase locked loop configured to generate a first clock of a first voltage domain;

a peripheral block, an audio block, a display block, a graphic block, an image processing block, and a codec block operating in response to the first clock;

a level shifter configured to generate a second clock of a second voltage domain based upon the first clock; and

a processor operating in response to the second clock,

wherein the level shifter includes first and second voltage shifter circuits that are configured to have a same structure and are connected in parallel between an input node and an output node.

8. The system-on-chip as claimed in claim 7, wherein the first voltage shifter circuit comprises a first inverter and a second inverter connected in series and configured to operate at the second voltage domain, and

wherein the second voltage shifter circuit includes a third inverter configured to operate at the first voltage domain, and a fourth inverter configured to operate at the second voltage domain.

9. The system-on-chip as claimed in claim 7, wherein a voltage of the second voltage domain is higher in level than that of the first voltage domain.

10. A multimedia device, comprising:

a processor;

a working memory of the processor;

a modem configured to communicate with an exterior according to a control of the processor;

a storage unit configured to store data according to a control of the processor;

an user interface configured to sense an external signal and to transfer the sensed signal to the processor;

a display control unit configured to display an image via a display unit according to a control of the processor;

a sound control unit configured to output a sound via a speaker according to a control of the processor;

a codec unit configured to perform encoding and decoding operations according to a control of the processor;

a clock generating unit configured to generate a clock according to an output of an oscillator;

a phase locked loop configured to generate a first clock of a first voltage domain synchronized with the clock; and

a level shifter configured to generate a second clock of a second voltage domain in response to the first clock,

wherein the processor operates in response to the second clock, and

wherein the level shifter includes the first and second voltage shifter circuits that are configured to have a same structure and are connected in parallel between an input node and an output node.

11. The multimedia device as claimed in claim 10, wherein the level shifter comprises:

a first inverter configured to output a second voltage of the second voltage domain or a ground voltage according to a voltage of the input node;

a second inverter configured to output the second voltage or the ground voltage to the output node according to an output of the first inverter,

a third inverter configured to output the first voltage of the first voltage domain or the ground voltage according to a voltage of the input node; and

a fourth inverter configured to output the second voltage or the ground voltage to the output node according to an output of the third inverter.

12. The multimedia device as claimed in claim 10, wherein the processor, the working memory, the display control unit, the sound control unit, the codec unit, and the phase locked loop constitute a system-on-chip, and

wherein the working memory, the display control unit, the sound control unit, and the codec unit operate in response to the first clock.

13. The multimedia device as claimed in claim 10, further comprising:

an image processing unit configured to process image data taken via a camera according to a control of the processor.

14. The multimedia device as claimed in claim 13, wherein the processor, the display control unit, the sound control unit, the image processing unit, the working memory, the codec unit, and the phase locked loop constitute a system-on-chip, and

wherein the working memory, the display control unit, the sound control unit, the image processing unit, and the codec unit operate in response to the first clock.

15. The multimedia device as claimed in claim 13, wherein the processor, the display control unit, the sound control unit, the modem, the image processing unit, the working memory, the codec unit, and the phase locked loop are included together as a system-on-chip, and

wherein the display control unit, the sound control unit, the modem, the image processing unit, the working memory, and the codec unit operate in response to the first clock.

16. The multimedia device as claimed in claim 13, wherein the processor, the display control unit, the sound control unit, the working memory, the codec unit, and the phase locked loop are included together as a system-on-chip, and

wherein the display control unit, the sound control unit, the working memory, and the codec unit operate in response to the first clock.

17. The multimedia device as claimed in claim 13, wherein the processor, the display control unit, the sound control unit, the working memory, and the phase locked loop are included together as a system-on-chip, and

wherein the display control unit, the sound control unit, and the working memory operate in response to the first clock.

18. The multimedia device as claimed in claim 13, wherein the processor, the display control unit, the working memory, and the phase locked loop are included together as a system-on-chip, and

wherein the display control unit and the working memory operate in response to the first clock.

19. The multimedia device as claimed in claim 13, wherein:

the processor, the working memory, and the phase locked loop are included together as a system-on-chip, and

the working memory operates in response to the first clock.

20. The multimedia device as claimed in claim 13, wherein the processor, the sound control unit, the working memory, and the phase locked loop are included as a system-on-chip, and

wherein the sound control unit and the working memory operate in response to the first clock.

21. The multimedia device as claimed in claim 13, wherein the processor, the working memory, modem, the storage unit, the user interface, the display control unit, the display unit, the sound control unit, the speaker, the oscillator, the clock generating unit, the camera, an image processing unit, the codec unit, and the phase locked loop are included in a mobile device.

22. The multimedia device as claimed in claim 13, wherein the processor, the working memory, modem, the storage unit, the user interface, the display control unit, the display unit, the sound control unit, the speaker, the oscillator, the clock generating unit, the camera, an image processing unit, the codec unit, and the phase locked loop are included in a smart television.

23. A level shifter, including:

a first voltage shifter circuit; and

a second voltage shifter circuit connected in parallel with the first voltage shifter circuit between an input node and an output node,

wherein;

a second clock of a second voltage domain is output from the output node in response to a first clock of a first voltage domain input at the input node, and

a delay time between a rising edge of the first clock and a rising edge of the second clock is identical to a delay time between a falling edge of the first clock and a falling edge of the second clock.