SEMICONDUCTOR DEVICE HAVING BIT LINES AND LOCAL I/O LINES

• US 20120120705A1
• Filed: 09/27/2011
• Published: 05/17/2012
• Est. Priority Date: 11/11/2010
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: FUJISAWA, Hiroki, MITSUBORI, Shingo
• Granted Patent: US 8,427,856 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/025 in signal lines

Abstract

The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.

Claims

1. A semiconductor device comprising:

a selection signal line supplied with a selection signal;

a plurality of first and second local I/O lines;

a plurality of first and second bit lines;

a plurality of first transistors each having a control electrode, each of the first transistors being coupled between an associated one of the first local I/O lines and an associated one of the first bit lines;

a plurality of second transistors each having a control electrode, each of the second transistors being coupled between an associated one of the second local I/O lines and an associated one of the second bit lines;

a first via conductor coupled between the selection signal line and the control electrodes of the first transistors;

a second via conductor coupled between the selection signal line and the control electrodes of the second transistors; and

a failure detecting circuit that detects a defect of at least one of the first and second via conductors by comparing a plurality of first data on the first local I/O lines read from the first bit lines and a plurality of second data on the second local I/O lines read from the second bit lines.

2. The semiconductor device as claimed in claim 1, wherein the failure detecting circuit includes:

a plurality of first comparing circuits each activating a comparison result signal when a logic level of an associated one of the first data is not coincident with a logic level of an associated one of the second data; and

a second comparing circuit activating a first detection signal when all of the comparison result signals are activated, the first detection signal indicating the defect of at least one of the first and second via conductors.

3. The semiconductor device as claimed in claim 2, wherein the failure detecting circuit further detects a defect of at least one of the first and second bit lines by comparing the first data and the second data.

4. The semiconductor device as claimed in claim 3, wherein the failure detecting circuit further includes a third comparing circuit activating a second detection signal when at least one of the comparison result signals is activated, the second detection signal indicating the defect of at least one the first and second bit lines.

5. The semiconductor device as claimed in claim 4, further comprising a test control circuit that outputs test result signals based on the first and second detection signals simultaneously to two different nodes when a test activation signal is activated.

6. The semiconductor device as claimed in claim 5, wherein the test control circuit includes:

a first logical gate circuit that receives the test activation signal via a first input signal line; and

a first switch circuit inserted into the first input signal line, the first switch circuit being controlled by the first decision signal.

7. The semiconductor device as claimed in claim 6, wherein the first switch circuit is brought into an on state when at least one of a plurality of the first decision signals is activated.

8. The semiconductor device as claimed in claim 5, wherein the test control circuit includes:

a second logical gate circuit that receives the test activation signal via a second input signal line; and

a second switch circuit inserted into the second input signal line, the second switch circuit being controlled by the second decision signal.

9. The semiconductor device as claimed in claim 8, wherein the second switch circuit is brought into an on state when at least one of a plurality of the second decision signals is activated.

10. The semiconductor device as claimed in claim 4, further comprising a test control circuit that selectively outputs test result signals based on the first and second detection signals to a predetermined node.

11. The semiconductor device as claimed in claim 10, wherein the test control circuit includes:

a third logical gate circuit that receives the test activation signal via third and fourth input signal lines;

a third switch circuit inserted into the third input signal line, the third switch circuit being controlled by the first decision signal; and

a fourth switch circuit inserted into the fourth input signal line, the fourth switch circuit being controlled by the second decision signal.

12. The semiconductor device as claimed in claim 11, wherein the third switch circuit is brought into an on state when at least one of a plurality of the first decision signals is activated.

13. The semiconductor device as claimed in claim 11, wherein the fourth switch circuit is brought into an on state when at least one of a plurality of the second decision signals is activated.

14. The semiconductor device as claimed in claim 2, further comprising a test control circuit that outputs test result signal based on the first detection signal to a first node.

15. The semiconductor device as claimed in claim 14, wherein the test control circuit includes:

a first OR gate circuit that receives a plurality of the first decision signals; and

a first latch circuit that receives an output signal of the first OR gate circuit and the test activation signal.

16. The semiconductor device as claimed in claim 15, wherein

the failure detecting circuit further includes a third comparing circuit activating a second detection signal when at least one of the comparison result signals is activated, the second detection signal indicating the defect of at least one the first and second bit lines, and

the test control circuit includes a second OR gate circuit that receives a plurality of the second decision signals, and a second latch circuit that receives an output signal of the second OR gate circuit and the test activation signal, thereby test result signal based on the second detection signal is supplied to a second node in response to the test activation signal.

17. The semiconductor device as claimed in claim 15, wherein

the failure detecting circuit further includes a third comparing circuit activating a second detection signal when at least one of the comparison result signals is activated, the second detection signal indicating the defect of at least one the first and second bit lines,

the test control circuit includes a second OR gate circuit that receives a plurality of the second decision signals, and

the first latch circuit further receives an output signal of the second OR gate circuit, thereby one of test result signals based on the first and second detection signals is selectively supplied to the first node in response to the test activation signal.

18. The semiconductor device as claimed in claim 1, wherein the selection signal line is physically single signal line.

19. A semiconductor device, comprising:

first to fourth memory cells;

first to fourth bit lines connected to the respective first to fourth memory cells;

first to fourth transistors connected to the respective first to fourth bit lines;

first to fourth lines connected to the respective first to fourth transistors;

a selection signal line including a first branch line diverged from the selection signal line and a second branch line diverged from the selection line, the first branch line being connected to gates of the first and second transistors, the second branch line being connected to gates of the third and fourth transistors;

a first comparator including a first input connected to the first and third lines; and

a second comparator including a second input connected to the second and fourth lines.

20. The semiconductor device as claimed in claim 19, further comprising:

a write circuit configured to write the same data into the first and fourth memory cells;

a read circuit configured to read a first value, a second value, a third value and fourth value from the first to fourth memory cells in which the same data is written, respectively, and transfer the first value to fourth values to the first to fourth lines, respectively; and

an AND circuit including an input connected to outputs of the first and second comparators.