Dual-Port Semiconductor Memory and First-In First-Out (FIFO) Memory Having Electrically Floating Body Transistor

• US 20120120752A1
• Filed: 11/15/2011
• Published: 05/17/2012
• Est. Priority Date: 11/16/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 8,582,359 B2
• Time in Patent Office: Days
• US Class Current: 365/230.05
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H10B 12/10 DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.

Claims

1. A multi-port semiconductor memory cell comprising:

a plurality of gates;

a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said memory cell; and

a plurality of conductive regions of a second conductivity type,

wherein one of the plurality of conductive regions separates each of the plurality of gates from the other of the plurality of gates.

2. The multi-port semiconductor memory cell of claim 1, wherein each of the plurality of gates is configured to provide at least one of read access from and write access to the multi-port semiconductor memory cell independent of the other of the plurality of gates.

3. The multi-port semiconductor memory cell of claim 1, wherein the multi-port semiconductor memory cell includes a total number of ports, a total number of gates, and a total number of conductive regions, wherein the total number of ports is equal to the total number of gates, and further wherein the total number of conductive regions is one more than the total number of gates.

4. The multi-port semiconductor memory cell of claim 1, wherein the plurality of conductive regions is in electrical communication with the common body region, and further wherein each of the plurality of conductive regions is spaced apart from the other of the plurality of conductive regions.

5. The multi-port semiconductor memory cell of claim 1, wherein at least a portion of the common body region separates each of the plurality of conductive regions from the other of the plurality of conductive regions.

6. The multi-port semiconductor memory cell of claim 1, wherein the plurality of conductive regions and the common body region form a plurality of diodes.

7. The multi-port semiconductor memory cell of claim 1, wherein the multi-port semiconductor memory cell includes a fin structure, and further wherein the fin structure includes the common body region.

8. The multi-port semiconductor memory cell of claim 7, wherein the fin structure is an elongate fin structure that includes a longitudinal axis, and further wherein the plurality of gates is spaced apart along the longitudinal axis.

10. The multi-port semiconductor memory cell of claim 1, wherein the multi-port semiconductor memory cell is formed on a substrate of the second conductivity type, wherein the substrate includes a substrate terminal configured to receive a substrate bias voltage, wherein the common body region is configured to retain a charge, and further wherein a maximum charge of the common body region increases with an increase in the substrate bias voltage.

11. The multi-port semiconductor memory cell of claim 1, wherein the multi-port semiconductor memory cell is formed on a substrate, wherein the multi-port semiconductor memory cell further includes a buried layer region, and further wherein the buried layer region separates the common body region from the substrate.

12. The multi-port semiconductor memory cell of claim 11, wherein the buried layer region includes an insulator layer that is configured to electrically isolate the common body region from the substrate.

13. The multi-port semiconductor memory cell of claim 11, wherein the buried layer region includes a conductive buried layer of the second conductivity type, and further wherein the substrate has the first conductivity type.

14. The multi-port semiconductor memory cell of claim 13, wherein the conductive buried layer, the common body region, and at least one of said conductive regions of a second conductivity type form a bipolar device.

15. The multi-port semiconductor memory cell of claim 13, wherein the common body region is configured to retain a charge, wherein the conductive buried layer includes a conductive buried layer terminal that is configured to receive a buried layer bias voltage, and further wherein the buried layer terminal is configured to at least one of inject a charge into and extract the charge out of the common body region to maintain said memory state of the semiconductor memory cell.

9. The multi-port semiconductor memory cell of 7, wherein the fin structure further includes the plurality of conductive regions.

16. (canceled)

17. A multi-port semiconductor memory cell comprising:

a plurality of ports;

a floating body transistor, wherein the floating body transistor includes a floating body region configured to store a charge that is indicative of the state of said memory cell; and

a plurality of access transistors, wherein each of the plurality of access transistors corresponds to a respective one of the plurality of ports.

18. The multi-port semiconductor memory cell of claim 17, wherein the floating body transistor is configured to receive an electric signal from a first access transistor of the plurality of access transistors and to provide the electric signal to a second access transistor of the plurality of access transistors.

19. A semiconductor memory cell comprising:

a plurality of transistors, wherein each of the plurality of transistors comprising;

a common body region configured to store a charge that is indicative of the state of said memory cell; and

a plurality of gates,

wherein said common body region is shared among the plurality of transistors, and further wherein said memory cell comprises a terminal configured to at least one of inject a charge into and extract the charge out of the common body region to maintain said memory state of the semiconductor memory cell.