FUSED MULTIPLY-ADD APPARATUS AND METHOD

• US 20120124117A1
• Filed: 06/06/2011
• Published: 05/17/2012
• Est. Priority Date: 11/17/2010
• Status: Active Grant

• Current Assignee: Industry Academic Cooperation Foundation, Samsung Electronics Co. Ltd.
• Original Assignee: Industry Academic Cooperation Foundation, Samsung Electronics Co. Ltd.
• Inventors: Yu, Hyeong-Seok, Suh, Dong-Kwan, Kim, Suk-Jin, Lee, Yong-Surk, Kim, San
• Granted Patent: US 8,805,915 B2
• Time in Patent Office: Days
• US Class Current: 708/205
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.

Claims

1. A fused multiply-add (FMA) apparatus comprising:

a partial product generator configured to generate a partial sum and a partial carry by dividing each of the mantissas of first and second floating-point numbers into a plurality of n-bit segments, computing partial products of the n-bit segments, and adding up the computed partial products;

a carry save adder configured to generate a partial sum that has a first bit size and a partial carry that has the first bit size by adding the partial sum and the partial carry to the least significant bits (LSBs) of a mantissa of a third floating-point number;

a carry select adder configured to generate a mantissa that has a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to the most significant bits (MSBs) of the third floating-point number; and

a first selector configured to transmit the partial sum and the partial carry to the carry save adder or the carry select adder based on whether the mantissa of the third floating-point number is zero.

2. The FMA apparatus of claim 1, further comprising:

a bit aligner configured to align the mantissa of the third floating-point number to the second bit size, output the LSBs of the mantissa of the third floating-point number to the carry save adder, and output the MSBs of the mantissa of the third floating-point number to the carry select adder;

a bit extender configured to extend the MSBs of the mantissa of the third floating-point number and output the extended MSBs to the carry select adder; and

a second selector configured to transmit the mantissa of the third floating-point number to the bit aligner or the bit extender based on whether the mantissa of the third floating-point number is zero.

3. The FMA apparatus of claim 1, further comprising:

a sign determiner configured to determine whether the second bit-size mantissa is signed or unsigned;

a complement generator configured to convert the second bit-size mantissa into its complement number if the second bit-size mantissa is signed;

a storage configured to store the second bit-size mantissa therein; and

a third selector configured to transmit the second bit-size mantissa to the complement generator or the storage based on whether the mantissa of the third floating-point number is zero.

4. The FMA apparatus of claim 3, further comprising:

is a normalizer configured to generate a mantissa that has a third bit size by normalizing the second bit-size mantissa stored in the storage to a third bit size;

a rounding determiner configured to determine whether the second bit-size mantissa has been rounded up during the normalization performed by the normalizer, wherein, if the second bit-size mantissa has been rounded up during the normalization performed by the normalizer, the rounding determiner outputs a predefined third bit-size mantissa; and

a fourth selector configured to select one of the third bit-size mantissa provided by the normalizer and the third bit-size mantissa provided by the rounding determiner.

5. The FMA apparatus of claim 4, further comprising:

a comparator configured to determine whether a number of LSBs of the second bit-size mantissa are all one and whether the second bit-size mantissa has been rounded up during the normalization performed by the normalizer; and

a fifth selector configured to select one of the third bit-size mantissa selected by the fourth selector and a third-bit size mantissa having all bits set to zero, based on the results of the determination performed by the comparator.

6. The FMA apparatus of claim 1, wherein the first bit size is two times greater than the bit size of a double-precision number.

7. The FMA apparatus of claim 1, wherein the second bit size is three times greater than the bit size of a double-precision number.

8. The FMA apparatus of claim 5, wherein the third bit size is the same as or greater than the bit size in of a mantissa of a double-precision number.

9. An FMA method comprising:

generating a partial sum and a partial carry by dividing each of the mantissas of first and second floating-point numbers into a plurality of n-bit segments, computing partial products of the n-bit segments, and adding up the computed partial products;

determining whether the mantissa of a third floating-point number is zero;

if the mantissa of the third floating-point number is zero, generating a partial sum that has a first bit size and a partial carry that has the first bit size by adding the partial sum and the partial carry to the LSBs of the mantissa of the third floating-point number, and extending the MSBs of the mantissa of the third floating-point number; and

generating a mantissa that has a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to the extended MSBs.

10. The FMA method of claim 9, further comprising:

determining whether the LSBs of the second bit-size mantissa are all one;

normalizing the second bit-size mantissa to a third bit size and determining whether the second bit-size mantissa has been rounded up; and

if the LSBs of the second bit-size mantissa are all one and the second bit-size mantissa has been rounded up, outputting a mantissa having the third bit size and that has all bits set to zero.

11. The FMA method of claim 9, wherein the first bit size is two times greater than is the bit size of a double-precision number.

12. The FMA method of claim 9, wherein the second bit size is three times greater than the bit size of a double-precision number.

13. The FMA method of claim 10, wherein the third bit size is the same as or greater than the bit size of a mantissa of a double-precision number.

14. A fused multiply-add (FMA) apparatus comprising:

a partial product generator that generates a partial product and a partial carry based on a mantissa of a first floating-point number and a mantissa of the second floating-point number;

a carry save adder that adds the partial sum and the partial carry to one or more least significant bits (LSBs) of a third floating-point number to generate a first bit-size partial sum and a first bit-size partial carry;

a carry select adder that adds the partial sum and partial carry to one or more most significant bits (MSBs) of the third floating point number or adds the first bit-size partial carry and the first bit-size partial sum to the one more MSBs of the third floating-point number, to generate a second bit-size partial sum and a second bit-size partial carry;

a storage that temporarily stores the second bit-size partial sum and the second bit-size partial carry; and

a selector that receives a signal that indicates whether the LSBs of the third floating-point number are zero, and determines whether to transmit the partial sum and the partial carry to the carry save adder or the carry select adder based on the received signal.

15. The FMA apparatus of claim 14, wherein if the selector receives a signal that indicates the LSBs of the third floating-point number are all zero, the selector skips the carry save adder and transmits the partial sum and the partial carry to the carry select adder.

16. The FMA apparatus of claim 14, wherein if the selector receives a signal that indicates the LSBs of the third floating-point number are not all zero, the selector transmits the partial sum and the partial carry to the carry save adder.