MULTICHIP MODULE FOR COMMUNICATIONS

• US 20120124257A1
• Filed: 11/17/2010
• Published: 05/17/2012
• Est. Priority Date: 11/17/2010
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wu, Ephrem C.
• Granted Patent: US 8,417,867 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/157 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/405 Physical details, e.g. power supply, mechanical construction or backplane of ATM switches

Abstract

An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks and the at least one crossbar switch to one another.

Claims

1. A multichip module, comprising:

a first transceiver die having first transceivers;

a second transceiver die having second transceivers;

a crossbar switch die having at least one crossbar switch;

a first protocol logic blocks die having first protocol logic blocks;

a second protocol logic blocks die having second protocol logic blocks; and

an interposer to which the first transceiver die, the second transceiver die, the crossbar switch die, the first protocol logic blocks die, and the second protocol logic blocks die are coupled;

wherein the first and second transceiver dice, the first and second protocol logic blocks dice, and the crossbar switch die are mounted on the interposer; and

wherein the interposer interconnects the first transceivers and the first protocol logic blocks to one another, interconnects the second transceivers and the second protocol logic blocks to one another, interconnects the first protocol logic blocks and the at least one crossbar switch to one another, and further interconnects the second protocol logic blocks and the at least one crossbar switch to one another.

3. The multichip module according to claim 1, wherein:

the first transceiver die, the first protocol logic blocks die, the second transceiver die, and the second protocol logic blocks die are all rectangular dice mounted to the interposer with a first orientation;

the first transceiver die and the first protocol logic blocks die are positioned on a left side of the crossbar switch die;

the second transceiver die and the second protocol logic blocks die are positioned on a right side of the crossbar switch die;

the first transceiver die is a leftmost outer die; and

the second transceiver die is a rightmost outer die.

4. The multichip module according to claim 3, further comprising:

a third transceiver die having third transceivers; and

a third protocol logic blocks die having third protocol logic blocks;

wherein the third transceiver die and the third protocol logic blocks die are coupled to the interposer; and

wherein the interposer interconnects the third transceivers and the third protocol logic blocks, and further interconnects the third protocol logic blocks and the at least one crossbar switch.

5. The multichip module according to claim 4, further comprising:

a fourth transceiver die having fourth transceivers; and

a fourth protocol logic blocks die having fourth protocol logic blocks;

wherein the fourth transceiver die and the fourth protocol logic blocks die are coupled to the interposer; and

wherein the interposer interconnects the fourth transceivers and the fourth protocol logic blocks, and further interconnects the fourth protocol logic blocks and the at least one crossbar switch.

6. The multichip module according to claim 5, wherein the first protocol logic blocks, the second protocol logic blocks, the third protocol logic blocks, and the fourth protocol logic blocks are all field programmable.

7. The multichip module according to claim 6, wherein:

the third transceiver die, the fourth transceiver die, the third protocol logic blocks die, and the fourth protocol logic blocks die are all rectangular dice mounted to the interposer with a second orientation;

the second orientation is at least substantially perpendicular to the first orientation;

the third transceiver die and the third protocol logic blocks die are positioned on a top side of the crossbar switch die;

the fourth transceiver die and the fourth protocol logic blocks die are positioned on a bottom side of the crossbar switch die;

the third transceiver die is a topmost outer die; and

the fourth transceiver die is a bottommost outer die.

8. The multichip module according to claim 7, wherein the first transceiver die, the second transceiver die, the third transceiver die, and the fourth transceiver die are respectively substantially longer than the first protocol logic blocks die, the second protocol logic blocks die, the third protocol logic blocks die, and the fourth protocol logic blocks die.

2. (canceled)

9. A system including the multichip module of claim 2, wherein:

the system includes a network switch having a backplane, a line card, and a switch card; and

the multichip module is mounted on either the line card or the switch card.

10. A method for communication, comprising:

receiving a packet by a first transceiver die of a multichip module;

providing the packet from the first transceiver die to a first protocol logic blocks die of the multichip module via an interposer;

wherein the interposer interconnects the first transceiver die and the first protocol logic blocks die to one another;

providing the packet from the first protocol logic blocks die to a crossbar switch die of the multichip module via the interposer;

wherein the interposer interconnects the first protocol logic blocks die and the crossbar switch die to one another;

providing the packet from the crossbar switch die to a second protocol logic blocks die of the multichip module via the interposer;

wherein the interposer interconnects the second protocol logic blocks die and the crossbar switch die to one another;

providing the packet from the second protocol logic blocks die to a second transceiver die of the multichip module via the interposer;

wherein the interposer interconnects the second protocol logic blocks die and the second transceiver die to one another; and

sending the packet from the second transceiver die out of the multichip module.

12. The method according to claim 10, further comprising:

instantiating in the first protocol logic blocks die a first ingress processing block to ingress process the packet according to a first protocol; and

instantiating in the second protocol logic blocks die a first egress processing block to egress process the packet according to the first protocol.

13. The method according to claim 12, further comprising:

instantiating in the first protocol logic blocks die a second ingress processing block to ingress process another packet according to a second protocol; and

instantiating in the second protocol logic blocks die a second egress processing block to egress process the other packet according to the second protocol;

wherein the first protocol and the second protocol are different protocols.

14. The method according to claim 13, wherein:

the first ingress processing block is instantiated in first programmable resources responsive to a first ingress processing block configuration bitstream;

the second ingress processing block is instantiated in second programmable resources responsive to a second ingress processing block configuration bitstream;

the first egress processing block is instantiated in third programmable resources responsive to a first egress processing block configuration bitstream; and

the second egress processing block is instantiated in fourth programmable resources responsive to a second egress processing block configuration bitstream.

15. The method according to claim 10, further comprising:

providing the packet from the crossbar switch die back to the first protocol logic blocks die of the multichip module via the interposer;

providing the packet from the first protocol logic blocks die back to the first transceiver die of the multichip module via the interposer; and

sending the packet from the first transceiver die out of the multichip module.

16. The method according to claim 15, further comprising instantiating, in the first protocol logic blocks die, an ingress processing block to ingress process the packet according to a protocol and an egress processing block to egress process the packet according to the protocol.

11. (canceled)

17. A multichip module, comprising:

a plurality of communication die;

a plurality of protocol logic blocks die;

a crossbar switch die; and

an interposer on which the at least one communication die, the at least one protocol logic blocks die, and the crossbar switch die are mounted;

wherein the interposer interconnects the at least one communication die, the at least one protocol logic blocks die, and the crossbar switch die for communication of information into and out of the multichip module via at least one of each of three types of die represented by the at least one communication die, the at least one protocol logic blocks die, and the crossbar switch die.

18. The multichip module according to claim 17, wherein:

a first number of the plurality of communication die and the plurality of protocol logic blocks die are mounted on the interposer with a first orientation;

a second number of the plurality of communication die and the plurality of protocol logic blocks die are mounted on the interposer with a second orientation; and

the first orientation is perpendicular or substantially perpendicular to the second orientation.

19. The multichip module according to claim 17, wherein:

the plurality of communication die is fabricated using a first semiconductor process; and

the plurality of protocol logic blocks die is fabricated using a second semiconductor process more advanced than the first semiconductor process.

20. The multichip module according to claim 19, wherein the crossbar switch die is fabricated using the second semiconductor process.