MICROCONTROLLER INCLUDING FLEXIBLE CONNECTIONS BETWEEN MODULES

• US 20120124261A1
• Filed: 11/15/2010
• Published: 05/17/2012
• Est. Priority Date: 11/15/2010
• Status: Active Grant

• Current Assignee: Atmel Rousset S.A.S. (Microchip Technology Incorporated)
• Original Assignee: Atmel Rousset S.A.S. (Microchip Technology Incorporated)
• Inventors: Vergnes, Alain, Tiennot, Renaud, Pean, Guillaume
• Granted Patent: US 8,601,197 B2
• Time in Patent Office: Days
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A microcontroller includes a system bus matrix to connect various modules. The microcontroller also includes direct connections between modules. For example, the microcontroller may include a direct connection between a data processing module and a memory controller module to improve the transfer rate for data that is processed by the data processing module.

Claims

1. A device comprising:

a processor, a plurality of modules, a system bus, and a direct connection, wherein;

the system bus is coupled to the processor and the modules;

the direct connection is coupled to a first module of the modules and a second module of the modules; and

the first module is configured to initiate a data transfer between the second module and the first module using the direct connection in response to receiving a request from a third module on the system bus.

2. The device of claim 1, wherein the first module is configured to perform data processing on data received from the second module resulting in processed data, and to output the processed data to the third module.

3. The device of claim 1, wherein the first module is configured to perform decryption of data received resulting in decrypted data and output the decrypted data to the third module.

4. The device of claim 1, wherein the first module is a data processing module.

5. The device of claim 1, wherein the third module is a display controller, and wherein the data transfers include transfers of image data.

6. The device of claim 1, wherein the third module includes an embedded Direct Memory Access (DMA) controller.

7. The device of claim 1, wherein the modules comprise one or more master modules and one or more slave modules, and wherein the system bus comprises a plurality of multiplexers configured to select connections between modules according to a plurality of signals from a master module initiating a data transfer.

8. The device of claim 1, further comprising a bus multiplexer module coupled to the second module, the direct connection to the first module, and the system bus, wherein the bus multiplexer module is configured to select between the system bus and the direct connection for the second module.

9. The device of claim 1, further comprising a bus multiplexer module coupled to the third module, the system bus, and the direct connection, wherein the bus multiplexer module is configured to select between the system bus and the direct connection for the third module.

10. The device of claim 1, wherein the second module is a memory controller.

11. The device of claim 10, wherein the memory controller is configured to receive read access commands on a plurality of inputs and process the read access commands in parallel.

12. The device of claim 10, wherein the memory controller comprises a queue for storing read access commands.

13. The device of claim 10, wherein the memory controller is coupled to an external memory having a latency greater than a clock cycle of the processor.

14. A method comprising:

initiating, using a first embedded direct memory access (DMA) module of a destination module, a first data transfer of data from a memory controller to a data processing module using a direct connection coupled to the memory controller and the data processing module;

processing the data using the data processing module; and

initiating a second data transfer from the data processing module to the destination module using a system bus coupled to the data processing module, the memory controller, and the destination module.

15. The method of claim 14, wherein the data is image data, processing the data includes decrypting the image data, and the destination module is a display controller module.

16. The method of claim 14, further comprising queuing read access requests at the memory controller.

17. The method of claim 14, wherein the memory controller is configured to receive read access commands on a plurality of inputs and process the read access commands in parallel.

18. The method of claim 14, wherein the destination module is a master module on the system bus and the memory controller module is a slave module on the system bus.

19. The method of claim 14, wherein initiating the first data transfer comprises configuring a plurality of multiplexers of the system bus by writing values to a plurality of configuration registers coupled to the multiplexers.