Decoding conditional program instructions

• US 20120124346A1
• Filed: 11/15/2010
• Published: 05/17/2012
• Est. Priority Date: 11/15/2010
• Status: Abandoned Application

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Hardage, James Nolan, Harris, Glen Andrew, Williamson, David James, Blasco Allue, Conrado
• Application Number:
  US12/926,395
• Publication Number:
  US 20120124346A1
• Time in Patent Office: Days
• US Class Current: 712/239
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect. If the condition prediction is incorrect, then the condition resolution circuitry flushes any micro-operation instructions associated with the conditional program instruction from the processing circuitry, changes the condition prediction to a new prediction and triggers the redecoding of the conditional program instruction in accordance with the new condition prediction.

Claims

1. Apparatus for processing data comprising:

instruction decoding circuitry configured to decode a program instruction to generate one or more micro-operation instructions;

processing circuitry configured to process said one or more micro-operation instructions, said processing circuitry including condition resolution circuitry configured to respond to a condition resolution micro-operation instruction to determine if a condition associated with said condition resolution micro-operation instruction is passed or failed;

wherein

at least one conditional program instruction specifying a processing action to be performed by said processing circuitry if a condition associated with said conditional program instruction is passed is decoded by said instruction decoding circuitry in accordance with a condition prediction as one of;

(i) in accordance with said condition prediction being a condition pass prediction, one or more micro-operation instructions that control said processing circuitry to perform said processing action together with a condition resolution micro-operation instruction; and

(ii) in accordance with said condition prediction being a condition fail, at least said condition resolution micro-operation instruction; and

said condition resolution circuitry is configured to respond to said condition resolution micro-operation instruction to determine if said condition prediction is incorrect and if said condition prediction is determined to be incorrect then;

(a) to flush any micro-operation instructions for said conditional program instruction from said processing circuitry;

(b) to change said condition prediction for said conditional program instruction to a new condition prediction; and

(c) to trigger said instruction decoding circuitry to decode said conditional program instruction again using said new condition prediction.

2. Apparatus as claimed in claim 1, wherein said instruction decoder is configured to decode said conditional program instruction in accordance with said condition prediction being a condition fail as a number of no-operation micro-operation instructions and said condition resolution micro-operation instruction, said number of no-operation micro-operation instructions being the same as a number of said one or more micro-operation instructions that control said processing circuitry to perform said processing action.

3. Apparatus as claimed in claim 1, wherein said condition resolution micro-operation instruction is a last micro-operation instruction in a sequence of micro-operations to which said conditional program instruction is decoded.

4. Apparatus as claimed in claim 1, wherein said conditional resolution micro-operation instruction is a conditional branch micro-operation instruction.

5. Apparatus as claimed in claim 4, wherein said condition resolution circuitry is conditional branch resolution circuitry.

6. Apparatus as claimed in claim 1, wherein conditional program instruction is single instruction multiple data program instruction and said processing action is performed upon multiple sets of operands.

7. Apparatus as claimed in claim 1, wherein said instruction decoding circuitry is configured to respond to a predication program instruction to predicate one or more other program instructions.

8. Apparatus as claimed in claim 7, wherein said conditional program instruction is a non-conditional program instruction predicated by said predication program instruction.

9. Apparatus as claimed in claim 8, wherein said conditional resolution circuitry returns at least some characteristics of said predication program instruction to said instruction decoding circuitry when triggering said instruction decoding circuitry to decode said conditional program instruction again using said new condition prediction.

10. Apparatus as claimed in claim 1, wherein said processing circuitry comprises a plurality of processing pipelines and said condition resolution circuitry is one of said plurality of processing pipelines.

11. Apparatus as claimed in claim 1, wherein said instruction decoding circuitry is configured to decode said conditional program instruction in accordance with said condition prediction being a condition fail, by generating said one or more micro-operation instructions that control said processing circuitry to perform said processing action and then suppressing sending of said one or more micro-operations instructions to said processing circuitry.

12. Apparatus as claimed in claim 11, wherein said one or more micro-operation instructions are replaced by a corresponding number of no-operation micro-operation instructions.

13. Apparatus for processing data comprising:

instruction decoding means for decoding a program instruction to generate one or more micro-operation instructions;

processing means for processing said one or more micro-operation instructions, said processing means including condition resolution means for responding to a condition resolution micro-operation instruction to determine if a condition associated with said condition resolution micro-operation instruction is passed or failed;

wherein

at least one conditional program instruction specifying a processing action to be performed by said processing means if a condition associated with said conditional program instruction is passed is decoded by said instruction decoding means in accordance with a condition prediction as one of;

(i) in accordance with said condition prediction being a condition pass prediction, one or more micro-operation instructions that control said processing means to perform said processing action together with a condition resolution micro-operation instruction; and

(ii) in accordance with said condition prediction being a condition fail, at least said condition resolution micro-operation instruction; and

said condition resolution means responds to said condition resolution micro-operation instruction to determine if said condition prediction is incorrect and if said condition prediction is determined to be incorrect then;

(a) to flush any micro-operation instructions for said conditional program instruction from said processing means;

(b) to change said condition prediction for said conditional program instruction to a new condition prediction; and

(c) to trigger said instruction decoding means to decode said conditional program instruction again using said new condition prediction.

14. A method of processing data comprising the steps of:

decoding a program instruction to generate one or more micro-operation instructions;

processing said one or more micro-operation instructions, said processing including condition resolution for responding to a condition resolution micro-operation instruction to determine if a condition associated with said condition resolution micro-operation instruction is passed or failed;

wherein

at least one conditional program instruction specifying a processing action to be performed if a condition associated with said conditional program instruction is passed is decoded in accordance with a condition prediction as one of;

(i) in accordance with said condition prediction being a condition pass prediction, one or more micro-operation instructions that control said processing action together with a condition resolution micro-operation instruction; and

(ii) in accordance with said condition prediction being a condition fail, at least said condition resolution micro-operation instruction; and

in response to said condition resolution micro-operation instruction, determining if said condition prediction is incorrect and if said condition prediction is determined to be incorrect then;

(a) to flush any micro-operation instructions for said conditional program instruction;

(b) to change said condition prediction for said conditional program instruction to a new condition prediction; and

(c) to trigger decoding said conditional program instruction again using said new condition prediction.

15. A method as claimed in claim 14, wherein said step of decoding decodes said conditional program instruction in accordance with said condition prediction being a condition fail as a number of no-operation micro-operation instructions and said condition resolution micro-operation instruction, said number of no-operation micro-operation instructions being the same as a number of said one or more micro-operation instructions that control said processing action.

16. A method as claimed in claim 14, wherein said condition resolution micro-operation instruction is a last micro-operation instruction in a sequence of micro-operations to which said conditional program instruction is decoded.

17. A method as claimed in claim 14, wherein said conditional resolution micro-operation instruction is a conditional branch micro-operation instruction.

18. A method as claimed in claim 14, wherein conditional program instruction is single instruction multiple data program instruction and said processing action is performed upon multiple sets of operands.

19. A method as claimed in claim 14, wherein said step of decoding responds to a predication program instruction to predicate one or more other program instructions.

20. A method as claimed in claim 19, wherein said conditional program instruction is a non-conditional program instruction predicated by said predication program instruction.

21. A method as claimed in claim 20, comprising returning at least some characteristics of said predication program instruction as inputs to decode said conditional program instruction again using said new condition prediction.

22. A method as claimed in claim 14, wherein said step of decoding decodes said conditional program instruction in accordance with said condition prediction being a condition fail, by generating said one or more micro-operation instructions that control said processing action and then suppressing further use of said one or more micro-operations instructions.

23. A method as claimed in claim 22, wherein said one or more micro-operation instructions are replaced by a corresponding number of no-operation micro-operation instructions.