Feedback Scan Isolation and Scan Bypass Architecture

• US 20120124433A1
• Filed: 11/11/2010
• Published: 05/17/2012
• Est. Priority Date: 11/11/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Policke, Paul F., Kim, Hong S., Bassett, Paul Douglas
• Granted Patent: US 8,627,159 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.

Claims

1. A scan isolation and bypass architecture comprising core logic having a core logic input and a core logic output;

an input isolation multiplexer having a first input, a second input, a selection input and an output, the input isolation multiplexer selectively providing one of the first and second inputs of the input isolation multiplexer to the output of the input isolation multiplexer based on the selection input of the input isolation multiplexer, the first input of the input isolation multiplexer being coupled to a functional input, the second input of the input isolation multiplexer being coupled to a functional output, the output of the input isolation multiplexer being coupled to the core logic input, and the selection input of the input isolation multiplexer being coupled to a first test select signal;

an output isolation multiplexer having a first input, a second input, a selection input and an output, the output isolation multiplexer selectively providing one of the first and second inputs of the output isolation multiplexer to the output of the output isolation multiplexer based on the selection input of the output isolation multiplexer, the first input of the output isolation multiplexer being coupled to the core logic output, the second input of the output isolation multiplexer being coupled to the output of the input isolation multiplexer, the output of the output isolation multiplexer providing the functional output, and the selection input of the output isolation multiplexer being coupled to a second test select signal;

wherein when the first and second test select signals indicate a core feedback test, the output isolation multiplexer passes the core logic output from the first input of the output isolation multiplexer to the output of the output isolation multiplexer as the functional output, and the input isolation multiplexer passes the core logic output from the second input of the input isolation multiplexer to the output of the input isolation multiplexer and the core logic input.

2. The scan isolation and bypass architecture of claim 1, wherein when the first and second test select signals indicate a bypass test, the input isolation multiplexer passes the functional input from the first input of the input isolation multiplexer to the output of the input isolation multiplexer, and the output isolation multiplexer passes the functional input from the second input of the output isolation multiplexer to the output of the output isolation multiplexer as the functional output.

3. The scan isolation and bypass architecture of claim 2, wherein when the first and second test select signals indicate a normal operation, the input isolation multiplexer passes the functional input from the first input of the input isolation multiplexer to the output of the input isolation multiplexer to be processed by the core logic, and the output isolation multiplexer passes the output of the core logic from the first input of the output isolation multiplexer to the output of the output isolation multiplexer as the functional output.

4. The scan isolation and bypass architecture of claim 2, further comprising an at-speed signal and input AND logic, the input AND logic comprising:

a first input coupled to the at-speed signal,

a second input coupled to the functional output, and

an output coupled to the second input of the input isolation multiplexer;

wherein when the at-speed signal has a first value the input AND logic passes the functional output to the output of the input AND logic, and when the at-speed signal has a second value the input AND logic prevents the functional output from passing to the output of the input AND logic.

5. The scan isolation and bypass architecture of claim 4, further comprising output AND logic comprising:

a first input coupled to the at-speed signal,

a second input coupled to the output of the input isolation multiplexer, and

an output coupled to the second input of the output isolation multiplexer;

wherein when the at-speed signal has the first value the output AND logic passes the output of the input isolation multiplexer to the output of the output AND logic, and when the at-speed signal has the second value the output AND logic prevents the output of the input isolation multiplexer from passing to the output of the output AND logic.

6. The scan isolation and bypass architecture of claim 2, further comprising an at-speed signal and output AND logic, the output AND logic comprising:

a first input coupled to the at-speed signal,

a second input coupled to the output of the input isolation multiplexer, and

an output coupled to the second input of the output isolation multiplexer;

wherein when the at-speed signal has a first value the output AND logic passes the output of the input isolation multiplexer to the output of the output AND logic, and when the at-speed signal has a second value the output AND logic prevents the output of the input isolation multiplexer from passing to the output of the output AND logic.

7. The scan isolation and bypass architecture of claim 1, wherein the functional input comprises N inputs and the functional output comprises M outputs, N being greater than M;

and wherein the scan isolation and bypass architecture further comprises;

exclusive-OR logic for reducing the number of functional inputs to equal the number of functional outputs, the exclusive-OR logic comprising;

an input coupled to the output of the input isolation multiplexer, and

an output coupled to the second input of the output isolation multiplexer, the output of the input isolation multiplexer being coupled to the second input of the output isolation multiplexer through the exclusive-OR logic.

8. The scan isolation and bypass architecture of claim 7, further comprising an at-speed signal and output AND logic, the output AND logic comprising:

a first input coupled to the at-speed signal,

a second input coupled to the output of the exclusive-OR logic, and

an output coupled to the second input of the output isolation multiplexer, the output of the exclusive-OR logic being coupled to the second input of the output isolation multiplexer through the output AND logic;

wherein when the at-speed signal has a first value the output AND logic passes the output of the exclusive-OR logic to the output of the output AND logic, and when the at-speed signal has a second value the output AND logic prevents the output of the exclusive-OR logic from passing to the output of the output AND logic.

9. The scan isolation and bypass architecture of claim 1, wherein the functional output comprises N outputs and the functional input comprises M inputs, N being greater than M;

and wherein the scan isolation and bypass architecture further comprises;

exclusive-OR logic for reducing the number of functional outputs to equal the number of functional inputs, the exclusive-OR logic comprising;

an input coupled to the functional output, and

an output coupled to the second input of the input isolation multiplexer, the functional output being coupled to the second input of the input isolation multiplexer through the exclusive-OR logic.

10. The scan isolation and bypass architecture of claim 9, further comprising an at-speed signal and input AND logic, the input AND logic comprising:

a first input coupled to the at-speed signal,

a second input coupled to the output of the exclusive-OR logic, and

an output coupled to the second input of the input isolation multiplexer, the output of the exclusive-OR logic being coupled to the second input of the input isolation multiplexer through the input AND logic;

wherein when the at-speed signal has a first value the input AND logic passes the output of the exclusive-OR logic to the output of the input AND logic, and when the at-speed signal has a second value the input AND logic prevents the output of the exclusive-OR logic from passing to the output of the input AND logic.

11. The scan isolation and bypass architecture of claim 1 incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

12. A scan isolation and bypass architecture comprising

core logic means for processing a core logic input to generate a core logic output;

an input selection means for passing one of a first input and a second input to an output based on a selection input, the first input of the input selection means being coupled to a functional input, the second input of the input selection means being coupled to a functional output, the output of the input selection means being coupled to the core logic input, and the selection input of the input selection means being coupled to a first test select signal;

an output selection means for passing one of a first input and a second input to an output based on a selection input, the first input of the output selection means being coupled to the core logic output, the second input of the output selection means being coupled to the output of the input selection means, the output of the output selection means providing the functional output, and the selection input of the output selection means being coupled to a second test select signal;

wherein when the first and second test select signals indicate a core feedback test, the output selection means passes the core logic output to the output of the output selection means as the functional output and the input selection means passes the core logic output to the output of the input selection means as the core logic input.

13. The scan isolation and bypass architecture of claim 12, wherein when the first and second test select signals indicate a bypass test, the input selection means passes the functional input to the output of the input selection means and the output selection means passes the functional input to the output of the output selection means as the functional output.

14. The scan isolation and bypass architecture of claim 13, wherein when the first and second test select signals indicate normal operation, the input selection means passes the functional input to the output of the input selection means to be processed by the core logic and the output selection means passes the output of the core logic to the output of the output selection means as the functional output.

15. A method of scan isolation and bypass testing for a core coupled to external logic, the core having core inputs and core outputs, the external logic providing functional inputs to the core inputs and accepting functional outputs from the core outputs, the method comprising:

causing the functional inputs from the external logic to bypass the core and pass to the functional outputs when a test selection signal indicates bypass testing;

causing the core outputs to feedback to the core inputs when the test selection signal indicates core logic feedback testing; and

causing the functional inputs to be processed by the core and the core outputs to pass to the external logic as the functional outputs when the test selection signal indicates normal processing.

16. The method of claim 15, further comprising:

providing the core outputs to the functional outputs when the test selection signal indicates core logic feedback testing.

17. The method of claim 15, further comprising:

blocking the feedback of the core outputs to the core inputs when an at-speed signal indicates the core logic inputs are not synchronized to receive the feedback from the core outputs.

18. The method of claim 17, further comprising:

blocking the functional inputs from the external logic from passing to the functional outputs when an at-speed signal indicates the external logic is not synchronized to receive the functional inputs.

19. The method of claim 15, further comprising:

blocking the functional inputs from the external logic from passing to the functional outputs when an at-speed signal indicates the external logic is not synchronized to receive the functional inputs.

20. The method of claim 15, wherein when there are more functional inputs than functional outputs, the method further comprising, when the test selection signal indicates bypass testing:

combining the functional inputs from the external logic to produce a reduced number of functional inputs equal to the number of functional outputs while bypassing the core, and

passing the reduced number of functional inputs to the functional outputs.

21. The method of claim 20, wherein the combining is done using exclusive-or logic.

22. The method of claim 20, further comprising:

blocking the reduced number of functional inputs from passing to the functional outputs when an at-speed signal indicates the external logic is not synchronized to receive the reduced number of functional inputs.

23. The method of claim 15, wherein when there are more functional outputs than functional inputs, the method further comprising, when the test selection signal indicates core logic feedback testing:

combining the core outputs to produce a reduced number of core outputs equal to the number of functional inputs, and

feeding back the reduced number of core outputs to the core inputs.

24. The method of claim 23, wherein the combining is done using exclusive-or logic.

25. The method of claim 23, further comprising:

blocking the feedback of the reduced number of core outputs to the core inputs when an at-speed signal indicates the core logic inputs are not synchronized to receive the feedback of the reduced number of core outputs.