SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND

• US 20120124446A1
• Filed: 01/24/2012
• Published: 05/17/2012
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T., Tsai, Victor Y., Feeley, Peter S.
• Granted Patent: US 8,352,833 B2
• Time in Patent Office: Days
• US Class Current: 714/756
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Claims

1. A memory system, comprising:

a master device configured to generate and transmit an activate signal, a timing signal, and a serial data in signal; and

a slave device comprising;

a serial peripheral interface NAND controller configured to receive the activate signal, the timing signal, and the serial data in signal, wherein the serial peripheral interface NAND controller is further configured to transmit the serial in data signal without translation into standard NAND format; and

a NAND memory configured to receive the serial data in signal transmitted from the serial peripheral interface NAND controller.

2. The memory system of claim 1, comprising a cache memory coupled to the serial peripheral interface NAND controller and the NAND memory, wherein the cache memory is configured to transmit data from the serial peripheral interface NAND controller to the NAND memory, and wherein the cache memory is further configured to transmit data from the NAND memory to the serial peripheral interface NAND controller.

3. The memory system of claim 1, comprising an error correction status register coupled to the serial peripheral interface NAND controller.

4. The memory system of claim 1, wherein the serial peripheral interface NAND controller is configured to perform error correction on data stored in the cache memory.

5. The memory system of claim 4, wherein performing error correction on data stored in the cache memory comprises:

reading data in the cache memory;

detecting errors in the data; and

updating an error correction status register.

6. The memory system of claim 4, wherein performing error correction on data stored in the cache memory comprises:

reading data in the cache memory;

detecting errors in the data;

correcting at least one error in the data; and

updating an error correction status register.

7. The memory system of claim 3, wherein the error correction status register is configured to store error types for the cache.

8. The memory system of claim 3, wherein the error correction status register is configured to store error correction enable and disable information.

9. The memory system of claim 3, wherein the error correction status register is configured to store information defining the size of the region on which the ECC algorithm is to be performed.

10. A memory device, comprising a serial peripheral interface (SPI) NAND controller configured to:

receive a serial data in signal, and

transmit the serial in data signal without translation into standard NAND format to a NAND memory.

11. The memory device of claim 10, comprising a cache memory, wherein the SPI NAND controller is configured to transmit the serial data in signal to the NAND memory via the cache memory.

12. The memory device of claim 11, wherein the cache memory is configured to transmit data output from the NAND memory to the SPI NAND controller, wherein the data has been checked by an error correction process.

13. The memory device of claim 12, comprising a cache memory, wherein the cache memory is configured SPI NAND controller is configured to transmit the serial data in signal to the NAND memory via the cache memory.

14. The memory device of claim 10, wherein the SPI NAND controller is configured to transmit the serial data in signal to the NAND memory as hexagonal operation signals.

15. A memory device, comprising:

a serial peripheral interface (SPI) NAND controller configured to;

receive a page address; and

modify the page address into a modified SPI NAND format; and

a NAND memory configured to receive the page address in the modified SPI NAND format.

16. The memory device of claim 15, comprising a cache memory, wherein the cache memory is configured to receive a data page associated with the page address from the NAND memory.

17. The memory device of claim 15, wherein the SPI NAND controller is configured to perform an error detection and correction algorithm on the data page stored in the cache memory to generate a corrected data page.

18. The memory device of claim 17, wherein performing the error detection and correction algorithm comprises using a linear block code, a BCH code, a Hamming code, or a Reed-Solomon code to detect and correct errors in the data.

19. The memory device of claim 17, comprising an error correction results register, wherein performing the error detection and correction algorithm includes updating the error correction results register.

20. The memory device of claim 17, wherein the SPI NAND controller is configured to transmit the corrected data page to a requesting device.