INTERCONNECTION STRUCTURES AND METHODS FOR TRANSFER-PRINTED INTEGRATED CIRCUIT ELEMENTS WITH IMPROVED INTERCONNECTION ALIGNMENT TOLERANCE

• US 20120126229A1
• Filed: 11/22/2011
• Published: 05/24/2012
• Est. Priority Date: 11/23/2010
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher
• Granted Patent: US 9,899,329 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/21 of an individual HDI interconnect
• CPC Class Codes: H01L 2224/2101 Structure
• CPC Class Codes: H01L 2224/2105 Shape
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/2405 Shape
• CPC Class Codes: H01L 2224/24101 Connecting bonding areas at the same height
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/244 Connecting portions
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82106 by subtractive methods
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/95001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

Claims

1. A method of assembling integrated circuit elements on a substrate, the method comprising:

providing integrated circuit elements on a receiving substrate, each of the integrated circuit elements comprising a chiplet substrate including a connection pad and a conductor element on a surface thereof, wherein the connection pad and the conductor element are electrically separated, and wherein at least one of the integrated circuit elements is misaligned on the receiving substrate relative to a desired position thereon such that the at least one of the integrated circuit elements is positioned on the receiving substrate at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; and

forming a conductive layer on the receiving substrate including the integrated circuit elements thereon such that the connection pad of each of the integrated circuit elements is electrically connected to the conductive layer notwithstanding that the at least one of the integrated circuit elements is misaligned on the receiving substrate.

2. The method of claim 1, wherein each of the integrated circuit elements includes an insulating layer on the chiplet substrate that exposes at least a portion of the connection pad to the conductive layer and covers the conductor element on the surface of each chiplet substrate to electrically separate the conductor element from the conductive layer.

3. The method of claim 2, wherein forming the conductive layer comprises:

forming a planarization layer including via openings therein on the receiving substrate including the integrated circuit elements thereon, wherein respective positions of the via openings in the planarization layer are based on respective desired positions of the integrated circuit elements on the receiving substrate; and

then

forming the conductive layer on the planarization layer and in the via openings to electrically contact the connection pad of each of the integrated circuit elements.

4. The method of claim 3, wherein at least one of the via openings exposes a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit elements that is misaligned on the receiving substrate.

5. The method of claim 2, wherein the connection pad of each of the integrated circuit elements is coupled to an active element therein such that the conductive layer provides an electrical connection between respective active elements of each chiplet substrate, and wherein the conductor element of each of the integrated circuit elements provides an electrical connection between respective active elements of a same chiplet substrate.

6. The method of claim 5, wherein each chiplet substrate includes a plurality of connection pads and a plurality of conductor elements, and wherein at least one of the conductor elements is provided between adjacent ones of the connection pads on the surface of each chiplet substrate.

7. The method of claim 2, wherein providing the integrated circuit elements on the receiving substrate comprises:

forming the integrated circuit elements including a plurality of active elements on a source substrate; and

transferring the integrated circuit elements from the source substrate to the receiving substrate such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.

8. The method of claim 7, wherein the source substrate includes a sacrificial layer thereon between the integrated circuit elements and the source substrate, and wherein transferring the integrated circuit elements comprises:

separating the integrated circuit elements from one another on the source substrate to define tethers attaching the integrated circuit elements to respective anchor areas on the source substrate; and

etching the sacrificial layer to release the integrated circuit elements from the source substrate without releasing the anchor areas therefrom.

9. The method of claim 8, wherein transferring further comprises:

pressing a stamp against the source substrate to break the tethers attaching the integrated circuit elements to the respective anchor areas;

retracting the stamp from the source substrate such that the integrated circuit elements are adhered to the stamp;

pressing the stamp including the integrated circuit elements thereon against the receiving substrate; and

retracting the stamp from the receiving substrate to delaminate the integrated circuit elements therefrom and such that the at least one of the integrated circuit elements is misaligned on the receiving substrate relative to the desired position.

10. The method of claim 8, further comprising:

forming a protective layer on the integrated circuit elements prior to separating and/or etching, the protective layer comprising a silicon dioxide layer and an amorphous silicon layer thereon.

11. An electronic component array, comprising:

a backplane substrate;

a plurality of integrated circuit elements on the backplane substrate, each of the integrated circuit elements comprising a chiplet substrate including a connection pad and a conductor element on a surface thereof, wherein the connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad, and wherein at least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon at a distance from the desired position that is greater than or equal to a distance between the conductor element and the connection pad; and

a plurality of conductive wires on the backplane substrate including the integrated circuit elements thereon, wherein the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding that the at least one of the integrated circuit elements is misaligned on the backplane substrate.

12. The array of claim 11, further comprising an adhesive layer between each of the chiplet substrates and the backplane substrate, wherein the adhesive layer adheres each of the chiplet substrates to the backplane substrate.

13. The array of claim 11, further comprising a planarization layer including via openings therein on the backplane substrate including the integrated circuit elements thereon, and wherein the conductive wires respectively extend into the via openings to electrically contact the connection pad of each of the integrated circuit elements.

14. The array of claim 13, wherein respective positions of the via openings in the planarization layer are based on respective desired positions of the integrated circuit elements on the backplane substrate, and wherein at least one of the via openings exposes a portion of the connection pad and a portion of the insulating layer covering the conductor element of the at least one of the integrated circuit element that is misaligned on the receiving substrate.

15. The array of claim 14, wherein the exposed portion of the connection pad is smaller than a dimension of the at least one via opening.

16. The array of claim 11, wherein the connection pad of each of the integrated circuit elements is coupled to an active element therein, wherein the conductive wires provide an electrical connection between respective active elements of each chiplet substrate, and wherein the conductor element of each of the integrated circuit elements provides an electrical connection between respective active elements of a same chiplet substrate.

17. The array of claim 16, wherein each chiplet substrate includes a plurality of connection pads and a plurality of conductor elements, and wherein at least one of the conductor elements is provided between adjacent ones of the connection pads on the surface of each chiplet substrate.

18. The array of claim 11, wherein the integrated circuit elements comprise transfer-printed elements.

19. The array of claim 11, wherein the conductor element and the connection pad on each chiplet substrate are portions of a same metal layer.

20. A structure for printing transferrable integrated circuit chiplets, comprising:

a substrate;

a patterned sacrificial layer on the substrate; and

a plurality of integrated circuit chiplets on the patterned sacrificial layer, wherein each of the plurality of integrated circuit chiplets includes;

a separate chiplet substrate detached from the substrate by a pattern of the sacrificial layer;

active elements on or in the chiplet substrate;

a connection pad on a surface of the chiplet substrate;

chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad;

a conductor electrically separate from the connection pad on the surface of the chiplet substrate, the conductor electrically connected to a chiplet wire or one of the active elements; and

an insulating layer on the chiplet substrate and the conductor, the insulating layer leaving at least a portion of the connection pad exposed.

21. The structure of claim 20, further comprising one or more test pads, a plurality of electrically conductive tethers, and anchors on the substrate, each anchor located over and in contact with the patterned sacrificial layer and having a tether connecting the anchor to one of the integrated circuit chiplets, wherein the tether electrically connects active elements in the one of the integrated circuit chiplets to one or more exposed electrical test pads in the anchor.

22. A method of fabricating transferrable integrated circuit chiplets, comprising:

forming a sacrificial layer on a substrate;

forming a chiplet substrate layer on the sacrificial layer;

forming active elements on or in the chiplet substrate layer;

forming a connection pad on a surface of the chiplet substrate layer;

forming chiplet wires on or in the chiplet substrate electrically connecting the active elements and the connection pad;

forming a conductor electrically separate from the connection pad on the surface of the chiplet substrate layer, the conductor electrically connected to a chiplet wire or active element;

forming an insulating layer over the chiplet substrate and the conductor, leaving at least a portion of the connection pad exposed; and

patterning the chiplet substrate layer and the sacrificial layer to form separate chiplet substrates detached from the substrate.

23. The method of claim 22, further comprising:

forming a protective layer on the insulating layer and the connection pad.

24. The method of claim 23, wherein the protective layer is a bi-layer, each layer of the bi-layer comprising a different material.

25. The method of claim 24, wherein the protective bi-layer includes a silicon dioxide layer and an amorphous silicon layer.