SEMICONDUCTOR DEVICE

• US 20120126249A1
• Filed: 02/02/2012
• Published: 05/24/2012
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: NAKANO, Yuki
• Granted Patent: US 9,293,575 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

Claims

1. A semiconductor device comprising:

a semiconductor layer made of SiC;

a source region formed in the semiconductor layer, the source region forming a surface of the semiconductor layer;

a body region formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench dug down in the semiconductor layer from the surface thereof, the gate trench passing through the source region and the body region and the deepest portion thereof reaches the drain region;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench on the gate insulating film;

a source trench dug down in the semiconductor layer from the surface thereof; and

a conductive material embedded in the source trench, the conductive material having a first layer conformal to a side surface and a bottom surface of the source trench and a second layer formed on the first layer.

2. The semiconductor device according to claim 1, wherein the source trench passes through the source region and the body region and the deepest portion thereof reaches the drain region.

3. The semiconductor device according to claim 1, wherein an ohmic contact is selectively formed between the first layer and the semiconductor layer.

4. The semiconductor device according to claim 1, wherein a non-ohmic contact is selectively formed between the first layer and the semiconductor layer.

5. The semiconductor device according to claim 1, wherein the second layer is made of Al.

6. The semiconductor device according to claim 1, wherein the conductive material further has an intermediate layer between the first and second layers.

7. The semiconductor device according to claim 6, wherein the intermediate layer contains Ti.

8. The semiconductor device according to claim 6, wherein the intermediate layer contains TiN.

9. The semiconductor device according to claim 6, wherein the intermediate layer has a laminating structure of Ti and TiN.

10. The semiconductor device according to claim 1, wherein the gate trench and the source trench have the same depth.

11. The semiconductor device according to claim 1, wherein the source trench is deeper than the gate trench.

12. The semiconductor device according to claim 1, wherein

the source region is an n⁺-type source region,

the drain region is an n-type drain region, and

the body region has a p-type region forming a side surface of the gate trench, and a p⁺-type region forming the side surface of the source trench and having an impurity concentration larger than that of the p-type region.

13. The semiconductor device according to claim 12, wherein an ohmic contact is selectively formed between the first layer and the n⁺-type source region.

14. The semiconductor device according to claim 1, wherein the first layer is made of polysilicon.

15. The semiconductor device according to claim 1, wherein the gate trench is formed to surround the source trench in plan view.

16. A semiconductor device comprising:

a semiconductor layer made of SiC;

a source region formed in the semiconductor layer, the source region forming a surface of the semiconductor layer;

a body region formed in the semiconductor layer, the body region being in contact with the source region from a side of a back surface of the semiconductor layer;

a drain region formed in the semiconductor layer, the drain region being in contact with the body region from the side of the back surface of the semiconductor layer;

a gate trench dug down in the semiconductor layer from the surface thereof, the gate trench passing through the source region and the body region and the deepest portion thereof reaches the drain region;

a gate insulating film formed on an inner surface of the gate trench;

a gate electrode embedded in the gate trench on the gate insulating film;

a source trench dug down in the semiconductor layer from the surface thereof; and

a conductive material embedded in the source trench, the conductive material selectively forming a first junction with respect to the semiconductor layer, the first junction having a smaller junction barrier than the diffusion potential of a body diode intrinsic in the semiconductor device.

17. The semiconductor device according to claim 16, wherein the source trench passes through the source region and the body region and the deepest portion thereof reaches the drain region.

18. The semiconductor device according to claim 16, wherein a non-ohmic contact is selectively formed between the conductive material and the semiconductor layer.

19. The semiconductor device according to claim 16, wherein the gate trench and the source trench have the same depth.

20. The semiconductor device according to claim 16, wherein the source trench is deeper than the gate trench.

21. The semiconductor device according to claim 16, wherein

the source region is an n⁺-type source region,

the drain region is an n-type drain region, and

the body region has a p-type region forming a side surface of the gate trench, and a p⁺-type region forming the side surface of the source trench and having an impurity concentration larger than that of the p-type region.

22. The semiconductor device according to claim 21, wherein an ohmic contact is selectively formed between the conductive material and the n⁺-type source region.

23. The semiconductor device according to claim 16, wherein the gate trench is formed to surround the source trench in plan view.