METHODS AND SYSTEMS FOR FABRICATION OF MEMS CMOS DEVICES IN LOWER NODE DESIGNS

• US 20120126433A1
• Filed: 11/21/2011
• Published: 05/24/2012
• Est. Priority Date: 11/19/2010
• Status: Abandoned Application

• Current Assignee: Baolab Microsystems SL
• Original Assignee: Baolab Microsystems SL
• Inventors: Montanya Silvestre, Josep
• Application Number:
  US13/300,882
• Publication Number:
  US 20120126433A1
• Time in Patent Office: Days
• US Class Current: 257/787
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps

Abstract

A method for manufacturing an integrated circuit including producing layers that form one or more electrical and/or electronic elements on a semiconductor material substrate. Then, producing ILD layers above the layers forming one or more electrical and/or electronic elements, including the steps of depositing a first layer of etch stopper material, depositing a second layer of dielectric material above and in contact with the first layer, forming at least one track extending through the first and second layers, and filling the at least one track with a non-metallic material.

Claims

1. A method for manufacturing an integrated circuit comprising:

producing layers that form one or more electrical and/or electronic elements on a semiconductor material substrate;

producing Inter Level Dielectric (ILD) layers above the layers forming the one or more electrical and/or electronic elements, wherein producing the ILD layers comprises;

depositing a first layer of etch stopper material;

depositing a second layer of dielectric material above and in contact with the first layer;

forming at least one track extending through the first and second layers; and

filling the at least one track with a non-metallic material.

2. The method of claim 1, further comprising forming at least one hollow space in the ILD layers by applying gaseous HF to at least a portion of the ILD layers including the at least one track.

3. The method of claim 1, wherein the at least one track includes a channel arranged to hold a metallic material for conducting electrical information to and from the one or more electrical and/or electronic elements.

4. The method of claim 1, wherein forming the at least one track includes etching the first and second layers.

5. The method of claim 1, wherein the etch stopper material includes silicon nitride.

6. The method of claim 1, wherein the dielectric material includes silicon oxide.

7. The method of claim 1, wherein the non-metallic material is capable of being etched by vapor HF.

8. The method of claim 7, wherein the non-metallic material includes silicon oxide.

9. The method of claim 1, wherein forming the at least one track includes forming the at least one track above a via space that is empty or holds metal.

10. The method of claim 1, wherein filling the at least one track with a non-metallic material is a result of a CMOS design rule violation.

11. The method of claim 1, wherein the one or more electrical and/or electronic elements have a feature size of 130 nm or lower.

12. The method of claim 1, wherein the integrated circuit is included in one of a handheld device, a mobile phone, a portable computing device, a computer tablet, and a wireless computing device.

13. The method of claim 1, wherein the integrated circuit is included in a motion sensor.

14. The method of claim 2, wherein at least a portion of a micro-electro-mechanical system (MEMS) is arranged in the integrated circuit.

15. The method of claim 14, wherein the portion of the MEMS is arranged in the hollow space in the ILD layers.

16. The method of claim 1, wherein the first and second layers are etched at substantially the same time using isotropic etching.

17. The method of claim 1, wherein the integrated circuit is manufactured using a CMOS manufacturing process.

18. The method of claim 1, wherein filling the at least one track with a non-metallic material is performed without requalification of a conventional CMOS manufacturing process.

19. The method of claim 14, wherein the MEMS comprises a conductor element including a movable part.

20. The method of claim 19, wherein the MEMS comprises at least two capacitor plates arranged to produce electrostatic fields over the movable part that are capable of moving the movable part.

21. The method of claim 19, wherein the MEMS operates as a relay, the MEMS comprising at least two contact points in an electric circuit arranged to allow the movable part to be in contact simultaneously with both contact points.

22. The method of claim 14, wherein the MEMS comprises a device including at least one of an electrical relay, accelerometer, gyroscope, inclinometer, Coriolis force detector, pressure sensor, microphone, flow rate sensor, temperature sensor, gas sensor, magnetic field sensor, electro-optical device, optical switching matrix, image projector device, analogue connection matrix, electromagnetic signal emission and/or reception device, power supply, DC/DC converter, AC/DC converter, DC/AC converter, A/D converter, D/A converter, and power amplifier.

23. The method of claim 19, wherein the at least one track defines one or more lateral edges of the first layer that are not in contact with a metallic material.

24. The method of claim 23, wherein the metallic material includes at least one of copper and aluminum.

25. A chip comprising an integrated circuit, said integrated circuit comprising:

one or more layers forming electrical and/or electronic elements on a semiconductor material substrate

one or more Inter Level Dielectric (ILD) layers above the layers forming the one or more electrical and/or electronic elements, the ILD layers comprising;

a first layer of etch stopper material;

a second layer of dielectric material above and in contact with the first layer;

at least one track extending through the first and second layers, wherein the at least one track is filled with a non-metallic material.

26. A method for manufacturing an integrated circuit comprising:

producing layers that form one or more electrical and/or electronic elements on a semiconductor material substrate;

producing Inter Level Dielectric (ILD) layers above the layers forming the one or more electrical and/or electronic elements, wherein producing the ILD layers comprises;

depositing a first layer of etch stopper material;

depositing a second layer of dielectric material above and in contact with the first layer;

forming a track extending through the first and second layers, the track defining one or more lateral edges of the first layer, wherein the one or more lateral edges are not in contact with a metallic material.

27. The method of claim 26, filling the track with a non-metallic material.

28. The method of claim 27, wherein the non-metallic material includes silicon oxide.

29. The method of claim 26, wherein forming the track includes forming the track above a via space that is empty or holds metal.

30. The method of claim 26, wherein filling the track with a non-metallic material is a result of a CMOS design rule violation.

31. The method of claim 26, wherein the metallic material includes at least one of copper and aluminum.

32. The method of claim 26, wherein forming the track includes etching the first and second layers.

33. The method of claim 26, wherein the etch stopper material includes silicon nitride.

34. The method of claim 26, wherein the dielectric material includes silicon oxide.

35. The method of claim 26, wherein the non-metallic material is capable of being etched by vapor HF.

36. The method of claim 26, wherein the one or more electrical and/or electronic elements have a feature size of 130 nm or lower.

37. The method of claim 26, wherein the integrated circuit is included in a handheld device, a mobile phone, a portable computing device, a computer tablet, and a wireless computing device.

38. The method of claim 26, wherein the integrated circuit is included in a motion sensor.

39. The method of claim 26, wherein at least a portion of a micro-electro-mechanical system (MEMS) is arranged in the integrated circuit.

40. A chip comprising an integrated circuit, said integrated circuit comprising:

one or more layers that form electrical and/or electronic elements on a semiconductor material substrate;

one or more Inter Level Dielectric (ILD) layers above the layers forming the one or more electrical and/or electronic elements, the ILD layers comprising;

a first layer of etch stopper material;

a second layer of dielectric material above and in contact with the first layer;

a first track extending through the first and second layers, the first track defining one or more lateral edges of the first layer, wherein the one or more lateral edges are not in contact with a metallic material.