SEMICONDUCTOR MEMORY DEVICE

• US 20120127781A1
• Filed: 11/16/2011
• Published: 05/24/2012
• Est. Priority Date: 11/24/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Granted Patent: US 8,854,865 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor

Abstract

To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell.

Claims

1. A semiconductor memory device comprising:

a bit line;

a word line;

n data lines (n is a natural number of 2 or more); and

a memory cell including a transistor and n capacitors, the transistor having a channel formed in an oxide semiconductor film,

wherein;

one of a source and a drain of the transistor is connected to the bit line;

the other of the source and the drain of the transistor is connected to one electrode of each of the n capacitors;

a gate of the transistor is connected to the word line; and

the other electrode of each of the n capacitors is connected to a corresponding one of the n data lines.

2. The semiconductor memory device according to claim 1, wherein capacitances of the n capacitors are different.

3. The semiconductor memory device according to claim 1, wherein a capacitance of a k-th capacitor of the n capacitors (k is a natural number of n or less) is 2^k-1 fold of a capacitance of a capacitor with a smallest capacitance.

4. The semiconductor memory device according to claim 3, wherein the capacitance of the capacitor with the smallest capacitance of the n capacitors is from 0.1 fF to 1 fF, inclusive.

5. The semiconductor memory device according to claim 1, comprising a plurality of memory cells, wherein the plurality of memory cells are stacked.

6. The semiconductor memory device according to claim 1, wherein a first capacitor of the n capacitors is provided in a first layer and a second capacitor of the n capacitors is provided in a second layer.

7. A semiconductor memory device comprising:

a bit line;

a word line;

a first data line formed on a first insulating film;

a second data line formed on a second insulating film; and

a memory cell including a transistor, a first capacitor with a first capacitance and a second capacitor with a second capacitance,

wherein one of a source and a drain of the transistor is connected to the bit line;

wherein the other of the source and the drain of the transistor is connected to one electrode of each of the first capacitor and the second capacitor;

wherein a gate of the transistor is connected to the word line;

wherein the other electrode of the first capacitor is connected to the first data line, and

wherein the other electrode of the second capacitor is connected to the second data line.

8. The semiconductor memory device according to claim 7, wherein the first capacitance is smaller than the second capacitance.

9. The semiconductor memory device according to claim 8, wherein the second capacitance is 2 fold of the first capacitance.

10. The semiconductor memory device according to claim 8, wherein the first capacitance is from 0.1 fF to 1 fF, inclusive.

11. The semiconductor memory device according to claim 7, comprising a plurality of memory cells, wherein the plurality of memory cells are stacked.

12. The semiconductor memory device according to claim 7, further comprising a third capacitor with a third capacitance and a third data line,

wherein the third data line is formed on the first insulating film, and

wherein the third capacitance is larger than the first capacitance and smaller than the second capacitance.

13. The semiconductor memory device according to claim 8, wherein the second data line is formed over the first data line.

14. A semiconductor memory device comprising:

a bit line;

a word line;

a first insulating film formed on a first electrode;

a first data line formed on the first insulating film;

a second insulating film formed on a second electrode;

a second data line formed on the second insulating film; and

a semiconductor layer,

wherein the bit line is electrically connected to the semiconductor layer;

wherein the first electrode and the second electrode is electrically connected to the semiconductor layer; and

wherein the word line is overlapping the semiconductor layer interposed with the first insulating film therebetween;

15. The semiconductor memory device according to claim 14, wherein a first capacitance between the first data line and the first electrode is smaller than a second capacitance between the second data line and the second electrode.

16. The semiconductor memory device according to claim 15, wherein the second capacitance is 2 fold of the first capacitance.

17. The semiconductor memory device according to claim 15, wherein the first capacitance is from 0.1 fF to 1 fF, inclusive.

18. The semiconductor memory device according to claim 15, further comprising a third data line formed on the first insulating film,

wherein a third capacitance between the third data line and the first electrode is larger than the first capacitance and smaller than the second capacitance.

19. The semiconductor memory device according to claim 14, wherein the second data line is formed over the first data line.

20. The semiconductor memory device according to claim 14, wherein the second electrode is electrically connected to the first electrode via a contact hole.