MEMORY WORD LINE BOOST USING THIN DIELECTRIC CAPACITOR

• US 20120127806A1
• Filed: 11/18/2010
• Published: 05/24/2012
• Est. Priority Date: 11/18/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: YU, Hung-Chang, CHIH, Yue-Der
• Granted Patent: US 8,369,180 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor.

Claims

1. A memory, comprising:

a word line; and

a word line boost circuit including;

a first capacitor having a first capacitor dielectric thickness; and

a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness,

wherein the word line boost circuit is configured to supply a first high voltage that is higher than a power supply voltage to the word line during a first operation of the memory by utilizing the first capacitor.

2. The memory of claim 1, wherein the word line boost circuit further comprises a pulse generator that supplies a pulse for the first capacitor.

3. The memory of claim 2, wherein the word line boost circuit further comprises a delay buffer coupled to the pulse generator and the first capacitor.

4. The memory of claim 2, wherein the word line boost circuit further comprises a second capacitor coupled to the pulse generator, the second capacitor having a second capacitor dielectric thickness that is greater than the first capacitor dielectric thickness.

5. The memory of claim 4, wherein the word line boost circuit further comprises a switch between the second capacitor and the word line.

6. The memory of claim 4, wherein the second capacitor is coupled to a bulk of a PMOS transistor of the transmission gate.

7. The memory of claim 4, wherein the first capacitor and the second capacitor are arranged to be coupled to ground during a second operation of the memory when a second high voltage that is higher than the first high voltage is supplied to the word line.

8. The memory of claim 1, wherein the memory further comprises a word line bias supply configured to supply a second high voltage that is higher than the first high voltage to the word line during a second operation of the memory.

9. A method for boosting a word line of a memory, comprising:

supplying a power supply voltage to a word line of the memory;

charging a first capacitor having a first capacitor dielectric thickness in a word line boost circuit to the power supply voltage; and

during a first operation of the memory, boosting a first voltage level of the word line to a first high voltage that is higher than the power supply voltage through a transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

10. The method of claim 9, further comprising supplying a pulse for the first capacitor.

11. The method of claim 10, further comprising:

delaying the pulse; and

supplying the delayed pulse to the first capacitor.

12. The method of claim 9, further comprising charging a second capacitor to the power supply voltage, the second capacitor having a second capacitor dielectric thickness greater than the first capacitor dielectric thickness.

13. The method of claim 12, further comprising supplying a pulse to the second capacitor.

14. The method of claim 13, further comprising during the first operation of the memory boosting a second voltage level of a bulk of a PMOS transistor in the transmission gate to a second high voltage, wherein the bulk is coupled to the second capacitor and the second high voltage is higher than the power supply voltage.

15. The method of claim 13, further comprising during the first operation of the memory, opening a switch coupled to the word line and the second capacitor.

16. The method of claim 9, further comprising during a second operation of the memory, supplying a second high voltage that is higher than the first high voltage to the word line.

17. The method of claim 16, further comprising during the second operation of the memory, isolating the first capacitor from the second high voltage.

18. The method of claim 16, wherein the isolating the first capacitor comprises turning off the transmission gate.

19. A memory, comprising:

a word line; and

a word line boost circuit including;

a first capacitor having a first capacitor dielectric thickness;

a pulse generator that supplies a pulse;

a delay buffer coupled to the pulse generator and the first capacitor;

a second capacitor coupled to the pulse generator, the second capacitor having a second capacitor dielectric thickness that is greater than the first capacitor dielectric thickness;

a switch coupled to the second capacitor and the word line; and

a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness;

wherein the second capacitor is coupled to a bulk of a PMOS transistor of the transmission gate, the switch is configured to be closed during a first operation of the memory, and the word line boost circuit is configured to supply a first high voltage that is higher than a power supply voltage to the word line during the first operation of the memory by utilizing the first capacitor.

20. The memory of claim 19, wherein the memory further comprises a word line bias supply configured to supply a second high voltage that is higher than the first high voltage to the word line during a second operation of the memory.