SENSE AMPLIFIER AND METHOD OF SENSING DATA USING THE SAME
First Claim
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1. A circuit comprising:
- a node having a node voltage;
a memory cell coupled to the node;
a first device coupled to the node;
a charge circuit coupled to the node; and
a feedback circuit coupled to the node,wherein during a pre-charge cycle of the memory cell;
the first device is configured to cause the node voltage to transition to a first voltage level,the charge circuit is configured to cause the node voltage to transition to a second voltage level after the node voltage equals the first voltage level, the second voltage level being different from the first voltage level; and
the feedback circuit is configured to selectively activate or deactivate the charge circuit in response to the node voltage.
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Abstract
Some embodiments regard a circuit comprising a pre-charge circuit and a latch circuit. The pre-charge circuit charges a voltage node to a pre-determined voltage level based on which the latch circuit generates a feedback signal to stop the pre-charge circuit from charging.
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Citations
20 Claims
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1. A circuit comprising:
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a node having a node voltage; a memory cell coupled to the node; a first device coupled to the node; a charge circuit coupled to the node; and a feedback circuit coupled to the node, wherein during a pre-charge cycle of the memory cell; the first device is configured to cause the node voltage to transition to a first voltage level, the charge circuit is configured to cause the node voltage to transition to a second voltage level after the node voltage equals the first voltage level, the second voltage level being different from the first voltage level; and the feedback circuit is configured to selectively activate or deactivate the charge circuit in response to the node voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A circuit comprising:
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a node having a node voltage; a first device coupled to the node; a memory cell coupled to the node; a charge circuit coupled to the node; a second device coupled to the node; a feedback circuit coupled to the node; and an output circuit coupled to the node and the feedback circuit, wherein during a first phase of a read cycle of the memory cell; the first device configured to cause the node voltage to transition to a first voltage level; and the second device and the memory cell are configured to be electrically disconnected from the node, wherein during a second phase of the read cycle; the charge circuit configured to cause the node voltage to transition to a second voltage level different from the first voltage level; and wherein during a third phase of the read cycle; the second device and the memory cell are configured to be electrically connected to the node; the feedback circuit configured to deactivate the charge circuit; and the output circuit configured to generate a read datum for the memory cell. - View Dependent Claims (11, 12, 13)
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14. A circuit comprising:
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an output circuit having an input node, the input node having an input node voltage level, and the output circuit being configured to generate an output signal having a first logic state during a period that the input node voltage level is equal to or greater than a trip voltage level of the output circuit and to generate the output signal having a second logic state during a period that the input node voltage level is less than the trip voltage level of the output circuit; a feedback circuit coupled to the output circuit and configured to generate a feedback control signal according to the output signal from the output circuit; and a charge circuit coupled to the feedback circuit for receiving the feedback control signal and coupled to the input node of the output circuit, the feedback circuit being configured to, via the feedback control signal, selectively activate the charge circuit to charge the input node or selectively deactivate the charge circuit in response to the output signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification