PCIE NVRAM CARD BASED ON NVDIMM

• US 20120131253A1
• Filed: 11/18/2011
• Published: 05/24/2012
• Est. Priority Date: 11/18/2010
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Nimble Storage Inc (Hewlett-Packard Enterprise Company)
• Inventors: Maheshwari, Umesh, McKnight, Thomas P., Zuo, Xiaoshan
• Granted Patent: US 8,949,502 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.

Claims

1. A memory system controller, comprising:

one or more sockets for accommodating NVDIMM cards;

a PCIe interface for coupling the memory system controller to a host;

a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections, said controller configured to;

manage data transfers between the host system and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as direct memory access (DMA) reads and writes,

format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and

initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications; and

power detection logic coupled to the PCIe interface and the controller and configured to detect and provide the controller with said power failure and power restoration indications.

2. The memory system controller of claim 1, wherein the controller comprises a field programmable gate array (FPGA).

3. The memory system controller of claim 2, wherein the FPGA includes a DMA engine configured to reformat data received over the PCIe bus to comply with DDR2 memory interface requirements for the NVDIMM.

4. The memory system controller of claim 1, wherein a first one of the NVDIMM sockets is a 240-pin NVDIMM DDR2 RDIMM socket, and a second one of the NVDIMM sockets is a 244-pin DDR2 Mini RDIMM socket.

5. The memory system controller of claim 1, further comprising resistor loads coupled to the controller for configuring the memory system controller according to installed NVDIMM devices.

6. The memory system controller of claim 1, wherein the controller is configured to issue two wire interface (TWI) write and read commands to the NVDIMM sockets.

7. The memory system controller of claim 1, wherein the controller is configured as PCIe-to-DDR interface logic between a PCIe end point and a DDR2 controller for managing register read and write operations, generating memory read requests to a host system for DMA operations, receiving completion packets for read requests generated, transmitting TLPs to a PCIe block, PCIe address management, SGL management, DMA descriptor management, managing read and write data buffers, and managing a DDR2 controller interface.

8. The memory system controller of claim 7, wherein the PCIe-to-DDR interface logic includes a system-to-card (S2C) DMA engine, which manages DMA write operations, and a card-to-system (C2S) DMA engine, which manages DMA read operations.

9. A method of controlling an NVDIMM, the method comprising:

at a controller of a memory system controller coupled to an NVDIMM, upon power up, checking a status of a nonvolatile memory controller of the NVDIMM to ensure the memory controller is initialized before valid data is stored in volatile memory of the NVDIMM

the controller of the memory system controller checking a status of nonvolatile memory on the NVDIMM to determine whether data previously stored in the in the nonvolatile memory is good or bad and, if required, initiating a restore operation;

if necessary, the controller of the memory system controller erasing the nonvolatile memory of the NVDIMM;

the controller of the memory system controller wait for back-up capacitors of the NVDIMM to charge to a threshold value before allowing a new set of write operations to start;

the controller of the memory system controller configuring an option to automatically save data in the volatile memory of the NVDIMM in the nonvolatile memory of the NVDIMM responsively to a power failure observed by the controller of the memory system controller; and

transferring data from a host system memory to the volatile memory of the NVDIMM and from volatile memory of the NVDIMM to the host system memory as direct memory access (DMA) operations under the control of the controller of the memory system controller while monitoring a status of power provided to the NVDIMM.