MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR RESPONDING HOST COMMAND

• US 20120131263A1
• Filed: 12/22/2010
• Published: 05/24/2012
• Est. Priority Date: 11/22/2010
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Yeh, Chih-Kang
• Granted Patent: US 8,392,649 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks

Abstract

A memory storage device, a memory controller thereof, and a method for responding host commands are provided. The memory storage device has a flash memory chip and a buffer memory. The present method includes receiving a write command issued by a host system and determining whether the write command causes the memory storage device to trigger a data moving procedure. If the write command does not cause the memory storage device to trigger the data moving procedure, the present method further includes sending an acknowledgement message corresponding to the write command to the host system after data corresponding to the write command is completely transferred to the buffer memory.

Claims

1. A method for responding host commands, adaptable to a memory storage device having a flash memory chip and a buffer memory, the method comprising:

receiving a write command from a host system;

determining whether the write command causes the memory storage device to trigger a data moving procedure; and

when the write command does not cause the memory storage device to trigger the data moving procedure, sending an acknowledgement message corresponding to the write command to the host system after a data corresponding to the write command is completely transferred to the buffer memory.

2. The method according to claim 1, wherein the data moving procedure comprises data moving operations incurred by merging physical blocks of the flash memory chip or data moving operations incurred by executing a wear leveling operation on the flash memory chip.

3. The method according to claim 1, wherein after the step of determining whether the write command causes the memory storage device to trigger the data moving procedure, the method further comprises:

when the write command causes the memory storage device to trigger the data moving procedure, sending the acknowledgement message to the host system after the data moving procedure is executed completely.

4. The method according to claim 1, wherein after the step of receiving the write command issued by the host system, the method further comprises:

setting a determination parameter to a first specific value.

5. The method according to claim 4 further comprising:

when the write command does not trigger the data moving procedure, setting the determination parameter to a second specific value; and

when the write command triggers the data moving procedure, setting the determination parameter to the second specific value after the data moving procedure is executed completely.

6. The method according to claim 5 further comprising:

when an interrupt command issued by the host system is received, determining the determination parameter is the first specific value or the second specific value;

when the determination parameter is the first specific value, not sending the acknowledgement message to the host system; and

when the determination parameter is the second specific value, sending the acknowledgement message to the host system.

7. The method according to claim 6, wherein the interrupt command is issued to the memory storage device when the host system determines that the data is completely transferred to the buffer memory.

8. A memory controller, comprising:

a host interface, for coupling a host system;

a memory interface, for coupling a flash memory chip;

a buffer memory; and

a memory management circuit, coupled to the host interface, the memory interface, and the buffer memory, for receiving a write command from the host system and determining whether the write command triggers a data moving procedure,

wherein when the write command does not trigger the data moving procedure, the memory management circuit further sends an acknowledgement message corresponding to the write command to the host system after a data corresponding to the write command is completely transferred to the buffer memory.

9. The memory controller according to claim 8, wherein the data moving procedure comprises data moving operations incurred by merging physical blocks of the flash memory chip or data moving operations incurred by executing a wear leveling operation on the flash memory chip.

10. The memory controller according to claim 8, wherein when the memory management circuit determines that the write command triggers the data moving procedure, the memory management circuit further sends the acknowledgement message to the host system after the data moving procedure is executed completely.

11. The memory controller according to claim 8, wherein the memory management circuit further sets a determination parameter to a first specific value after receiving the write command issued by the host system.

12. The memory controller according to claim 11, wherein the memory management circuit further sets the determination parameter to a second specific value when the write command does not trigger data moving procedure and sets the determination parameter to the second specific value after the data moving procedure is executed completely when the write command triggers the data moving procedure.

13. The memory controller according to claim 12, wherein the memory management circuit further determines the determination parameter is the first specific value or the second specific value when an interrupt command issued by the host system is received,

when the determination parameter is the first specific value, the memory management circuit does not send the acknowledgement message to the host system,

when the determination parameter is the second specific value, the memory management circuit sends the acknowledgement message to the host system.

14. The memory controller according to claim 13, wherein the interrupt command is issued to the memory management circuit when the host system determines that the data is completely transferred to the buffer memory.

15. A memory storage device, comprising:

a connector, for coupling a host system;

a flash memory chip; and

a memory controller, coupled to the flash memory chip and the connector, wherein the memory controller comprises a buffer memory,

the memory controller receives a write command issued by the host system and determines whether the write command triggers a data moving procedure,

when the write command does not trigger the data moving procedure, the memory controller further sends an acknowledgement message corresponding to the write command to the host system after a data corresponding to the write command is completely transferred to the buffer memory.

16. The memory storage device according to claim 15, wherein the data moving procedure comprises data moving operations incurred by merging physical blocks of the flash memory chip or data moving operations incurred by executing a wear leveling operation on the flash memory chip.

17. The memory storage device according to claim 15, wherein when the memory controller determines that the write command triggers the data moving procedure, the memory controller further sends the acknowledgement message to the host system after the data moving procedure is executed completely.

18. The memory storage device according to claim 15, wherein the memory controller further sets a determination parameter to a first specific value after receiving the write command issued by the host system.

19. The memory storage device according to claim 18, wherein the memory controller further sets the determination parameter to a second specific value when the write command does not trigger the data moving procedure and sets the determination parameter to the second specific value after the data moving procedure is executed completely when the write command triggers the data moving procedure.

20. The memory storage device according to claim 19, wherein the memory controller further determines the determination parameter is the first specific value or the second specific value when an interrupt command issued by the host system is received,

when the determination parameter is the first specific value, the memory controller does not send the acknowledgement message to the host system,

when the determination parameter is the second specific value, the memory controller sends the acknowledgement message to the host system.

21. The memory storage device according to claim 20, wherein the interrupt command is issued to the memory controller when the host system determines that the data is completely transferred to the buffer memory.