Data processing apparatus and method

• US 20120131312A1
• Filed: 09/22/2011
• Published: 05/24/2012
• Est. Priority Date: 11/23/2010
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Seal, David James, Grisenthwaite, Richard Roy, Stephens, Nigel John
• Granted Patent: US 9,207,937 B2
• Time in Patent Office: Days
• US Class Current: 712/208
• CPC Class Codes: G06F 7/764 Masking
• CPC Class Codes: G06F 7/768 Data position reversal, e.g. bit reversal, byte swapping
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A data processing apparatus 2 comprises a processing circuit 4 and instruction decoder 6. A bitfield manipulation instruction controls the processing apparatus 2 to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.

Claims

1. A data processing apparatus comprising:

processing circuitry configured to perform processing operations;

an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations;

wherein;

said program instructions include a bitfield manipulation instruction identifying at least a first source data value comprising at least one first source data element each having N bits <

N−

1;

0>

, a second source data value comprising at least one second source data element each having N bits <

N−

1;

0>

, and a control value;

said control value includes information for indicating a bitfield width W, a source bit position A and a result bit position B, where 1≦

W≦

N, 0≦

A≦

N−

W and 0≦

B≦

N−

W; and

said instruction decoder is responsive to said bitfield manipulation instruction to generate control signals for controlling said processing circuitry to generate a result data value comprising at least one result data element, each result data element corresponding to a corresponding first source data element and a corresponding second source data element, each result data element having N bits <

N−

1;

0>

comprising;

(a) bits <

B+W−

1;

B>

having bit values corresponding to bits <

A+W−

1;

A>

of said corresponding first source data element; and

(b) if B+W<

N, bits <

N−

1;

B+W>

having bit values corresponding to a prefix value selected, in dependence on said control value, as one of (i) a first prefix value comprising bits each having a zero value, (ii) a second prefix value having the bit values of bits <

N−

1;

B+W>

of said corresponding second source data element, and (iii) a third prefix value having bit values corresponding to a sign extension of bits <

A+W−

1;

A>

of said corresponding first source data element.

2. The data processing apparatus according to claim 1, wherein said third prefix value comprises bits each having the bit value of bit <

A+W−

1>

of said corresponding first source data element.

3. The data processing apparatus according to claim 1, wherein if B>

0, then each result data element further comprises bits <

B−

1;

0>

having bit values corresponding to a suffix value selected, in dependence on said control value, as one of (i) a first suffix value comprising bits each having a zero value, and (ii) a second suffix value having the bit values of bits <

B−

1;

0>

of said corresponding second source data element.

4. The data processing apparatus according to claim 1, comprising a plurality of storage locations configured to store data values for processing by said processing circuitry;

wherein said bitfield manipulation instruction identifies at least a first source storage location for storing said first source data value, and a destination storage location; and

said instruction decoder is responsive to said bitfield manipulation instruction to generate control signals for controlling said processing circuitry to store said result data value in said destination storage location.

5. The data processing apparatus according to claim 4, wherein said second source data value is a data value stored in said destination storage location prior to execution of said bitfield manipulation instruction.

6. The data processing apparatus according to claim 4, wherein said plurality of storage locations are accessible as storage locations of a plurality of different storage location sizes, and said control value includes information for identifying a storage location size of said first source storage location and said destination storage location.

7. The data processing apparatus according to claim 1, wherein said at least one first source data element, said at least one second source data element and said at least one result data element have a data element size N selected from a plurality of different data element sizes, and said control value includes information for identifying said data element size N.

8. The data processing apparatus according to claim 1, wherein said bitfield manipulation instruction has a bitfield insertion form wherein said source bit position A=0 and said result bit position B>

0, and a bitfield extraction form wherein said source bit position A≧

0 and said result bit position B=0.

9. The data processing apparatus according to claim 8, wherein said control value specifies a most significant bit position S and a rotation parameter R for determining said bitfield width W, said source bit position A and said result bit position B;

if S≧

R, then said source bit position A=R and said result bit position B=0, said bitfield width. W=(S+1)−

R and said bitfield manipulation instruction has said bitfield extraction form; and

if S<

R, then said source bit position A=0 and said result bit position B=N−

R, said bitfield width W=S+1, and said bitfield manipulation instruction has said bitfield insertion form.

10. The data processing apparatus according to claim 9, wherein said control value includes a first portion and a second portion each comprising a variable number of bits;

and

at least one of said instruction decoder and said processing circuitry is responsive to said bitfield manipulation instruction to determine the number of bits comprised by said first portion of said control value, and to determine based on the number of bits comprised by said first portion;

(a) a data element size N of said at least one first source data element, said at least one second source data element and said at least one result data element; and

(b) which bits of said second portion indicate said most significant bit position S and said rotation parameter R.

11. The data processing apparatus according to claim 1, wherein if said first source data value comprises a plurality of first source data elements, said second source data value comprises a plurality of second source data elements and said result data value comprises a plurality of result data elements, then said control value includes data element ordering information for indicating an order with which said plurality of result data elements are arranged within said result data value.

12. The data processing apparatus according to claim 11, wherein if said first source data value comprises a plurality of first source data elements, said second source data value comprises a plurality of second source data elements and said result data value comprises a plurality of result data elements, then said result data value is equivalent to a first data value obtained by:

(a) generating an intermediate value comprising said result data elements ordered corresponding to the order of the corresponding first source data elements in said first source data value and the order of the corresponding second source data elements in said second source data value, and

(b) performing at least one reordering iteration on said result data elements within said intermediate value to generate said first data value;

each reordering iteration comprising determining whether a corresponding bit of said data element ordering information has a predetermined value, and if said corresponding bit of said data element ordering information has said predetermined value then exchanging pairs of groups of bits within said intermediate value.

13. The data processing apparatus according to claim 12, wherein said groups of bits within said intermediate value comprise numbers of bits that are multiples of a data element size N of said at least one first source data element, said at least one second source data element and said at least one result data element.

14. The data processing apparatus according to claim 12, wherein said groups of bits comprise different numbers of bits for different ones of said at least one reordering iteration.

15. The data processing apparatus according to claim 11, wherein:

said control value includes a first portion and a second portion each comprising a variable number of bits; and

at least one of said instruction decoder and said processing circuitry is responsive to said bitfield manipulation instruction to determine the number of bits comprised by said first portion of said control value, and to determine based on the number of bits comprised by said first portion;

(a) a data element size N of said at least one first source data element, said at least one second source data element and said at least one result data element; and

(b) which bits of said second portion indicate said data element ordering information.

18. A virtual machine provided by a computer program which, when executed by a computer, provides an instruction execution environment according to the data processing apparatus as claimed in claim 1.

16. A data processing apparatus comprising:

processing means for performing processing operations;

instruction decoding means for generating, in response to program instructions, control signals for controlling said processing circuitry to perform said processing operations;

wherein;

said program instructions include a bitfield manipulation instruction identifying at least a first source data value comprising at least one first source data element each having N bits <

N−

1;

0>

, a second source data value comprising at least one second source data element each having N bits <

N−

1;

0>

, and a control value;

said control value includes information for indicating a bitfield width W, a source bit position A and a result bit position B, where 1≦

W≦

N, 0≦

A≦

N−

W and 0≦

B≦

N−

W; and

said instruction decoding means is responsive to said bitfield manipulation instruction to generate control signals for controlling said processing means to generate a result data value comprising at least one result data element, each result data element corresponding to a corresponding first source data element and a corresponding second source data element, each result data element having N bits <

N−

1;

0>

comprising;

(a) bits <

B+W−

1;

B>

having bit values corresponding to bits <

A+W−

1;

A>

of said corresponding first source data element; and

(b) if B+W<

N, bits <

N−

1;

B+W>

having bit values corresponding to a prefix value selected, in dependence on said control value, as one of (i) a first prefix value comprising bits each having a zero value, (ii) a second prefix value having the bit values of bits <

N−

1;

B+W>

of said corresponding second source data element, and (iii) a third prefix value having bit values corresponding to a sign extension of bits <

A+W−

1;

A>

of said corresponding first source data element.

17. A data processing method for a processing apparatus for performing processing operations, the method comprising:

in response to a bitfield manipulation instruction identifying at least a first source data value comprising at least one first source data element each having N bits <

N−

1;

0>

, a second source data value comprising at least one second source data element each having N bits <

N−

1;

0>

, and a control value, generating control signals for controlling said processing apparatus to generate a result data value comprising at least one result data element each having N bits <

N−

1;

0>

, each result data element corresponding to a corresponding first source data element and a corresponding second source data element;

wherein;

said control value includes information for indicating a bitfield width W, a source bit position A and a result bit position B, where 1≦

W≦

N, 0≦

A≦

N−

W and 0≦

B≦

N−

W, and each result data element comprises;

(a) bits <

B+W−

1;

B>

having bit values corresponding to bits <

A+W−

1;

A>

of said corresponding first source data element; and

(b) if B+W<

N, bits <

N−

1;

B+W>

having bit values corresponding to a prefix value selected, in dependence on said control value, as one of (i) a first prefix value comprising bits each having a zero value, (ii) a second prefix value having the bit values of bits <

N−

1;

B+W>

of said corresponding second source data element, and (iii) a third prefix value having bit values corresponding to a sign extension of bits <

A+W−

1;

A>

of said corresponding first source data element.

19. A data processing apparatus comprising:

processing circuitry configured to perform processing operations;

an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations;

wherein;

said program instructions include at least one instruction specifying a control value having a first portion for indicating a selected data size selected from a plurality of data sizes and a second portion for indicating at least one control parameter having a number of bits that varies in dependence on said selected data size, said first portion and said second portion each having a variable number of bits; and

said instruction decoder is responsive to said at least one instruction to generate control signals for controlling said processing circuitry to perform a corresponding processing operation in dependence on said selected data size and said at least one control parameter;

wherein when processing said at least one instruction, at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value and, in dependence on said number of bits comprised by said first portion, to identify (a) said selected data size, and (b) which bits of said control value form said second portion for indicating said at least one control parameter.

20. The data processing apparatus according to claim 19, wherein the number of bits of said first portion increases in dependence on said selected data size as the number of bits of said second portion decreases in dependence on said selected data size.

21. The data processing apparatus according to claim 19, wherein for at least a subset of said plurality of data sizes, said first portion comprises at least a first bit having a first state and X remaining bits having a second state, where X is a variable integer greater than, or equal to, 0;

and

said at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value in dependence on a bit position of said first bit within a predetermined portion of said control value.

22. The data processing apparatus according to claim 21, wherein said first portion comprises at least one additional bit for providing further information for identifying said selected data size.

23. The data processing apparatus according to claim 19, wherein said at least one control parameter comprises a plurality of control parameters;

and

when processing said at least one instruction, said at least one of said instruction decoder and said processing circuitry is configured to identify, in dependence on said number of bits comprised by said first portion, which bits of said second portion indicate each of said plurality of control parameters.

24. The data processing apparatus according to claim 23, wherein said plurality of control parameters comprise at least a first control parameter having a number of bits that increases as said selected data size increases, and a second control parameter having a number of bits that decreases as said selected data size increases;

and

said second portion includes a sub-portion for indicating said first control parameter and said second control parameter, said at least one of said instruction decoder and said processing circuitry identifying, in dependence on said number of bits comprised by said first portion, which bits of said sub-portion indicate said first control parameter and which bits of said sub-portion indicate said second control parameter.

25. The data processing apparatus according to claim 19, wherein said at least one instruction includes at least one single-instruction-multiple-data (SIMD) instruction identifying a source data value comprising at least one source data element;

and

for said at least one SIMD instruction said selected data size indicates a data element size of said at least one source data element, and said corresponding processing operation comprises performing a selected processing operation on each of said at least one source data element of said source data value.

26. The data processing apparatus according to claim 25, wherein said at least one SIMD instruction includes a bitfield manipulation instruction and for said bitfield manipulation instruction:

said corresponding processing operation comprises generating a result data value comprising at least one result data element, each result data element corresponding to a corresponding source data element of said source data value;

each result data element comprises a result bitfield having bit values corresponding to bit values of a source bitfield of consecutive bits within said corresponding source data element; and

said at least one control parameter indicates the number of bits comprised by said source bitfield and said result bitfield, a position of said source bitfield within said corresponding source data element, and a position of said result bitfield within said result data element.

27. The data processing apparatus according to claim 26, wherein for said bitfield manipulation instruction, if said source data value comprises a plurality of source data elements and said result data value comprises a plurality of result data elements, then said at least one control parameter also includes a data element ordering parameter for indicating an order with which said plurality of result data elements are arranged within said result data value.

28. The data processing apparatus according to claim 19, wherein said at least one instruction includes a bitwise logical instruction identifying a source data value;

and for said bitwise logical instruction;

said corresponding processing operation comprises generating a result data value equivalent to the result of applying a logical operation to said source data value and a second data value determined based on said control value;

said selected data size indicates a number of bits comprised by a repeating pattern of bits within said second data value; and

said at least one control parameter indicates information for identifying bit values of said repeating pattern of bits.

29. The data processing apparatus according to claim 28, wherein said bitwise logical operation comprises one of an AND operation, an OR operation and an exclusive OR operation.

32. A virtual machine provided by a computer program which, when executed by a computer, provides an instruction execution environment according to the data processing apparatus as claimed in claim 19.

30. A data processing apparatus comprising:

processing means for performing processing operations;

instruction decoding means for, in response to program instructions, generating control signals for controlling said processing means to perform said processing operations;

wherein;

said program instructions include at least one instruction specifying a control value having a first portion for indicating a selected data size selected from a plurality of data sizes and a second portion for indicating at least one control parameter having a number of bits that varies in dependence on said selected data size, said first portion and said second portion each having a variable number of bits; and

said instruction decoding means is responsive to said at least one instruction to generate control signals for controlling said processing means to perform a corresponding processing operation in dependence on said selected data size and said at least one control parameter;

wherein when processing said at least one instruction, at least one of said instruction decoding means and said processing means is configured to identify the number of bits comprised by said first portion of said control value and, in dependence on said number of bits comprised by said first portion, to identify (a) said selected data size, and (b) which bits of said control value form said second portion for indicating said at least one control parameter.

31. A data processing method for a processing apparatus for performing processing operations in response to program instructions, comprising:

receiving at least one instruction specifying a control value having a first portion for indicating a selected data size selected from a plurality of data sizes and a second portion for indicating at least one control parameter having a number of bits that varies in dependence on said selected data size, said first portion and said second portion each having a variable number of bits;

in response to said at least one instruction, identifying the number of bits comprised by said first portion of said control value;

in dependence on said number of bits comprised by said first portion, identifying (a) said selected data size, and (b) which bits of said control value form said second portion for indicating said at least one control parameter; and

controlling said processing apparatus to perform a corresponding processing operation in dependence on said selected data size and said at least one control parameter.