VERIFICATION APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND VERIFICATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20120131536A1
• Filed: 07/15/2011
• Published: 05/24/2012
• Est. Priority Date: 11/24/2010
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KITAZAWA, Tomoko
• Application Number:
  US13/184,460
• Publication Number:
  US 20120131536A1
• Time in Patent Office: Days
• US Class Current: 716/136
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking

Abstract

A verification apparatus for a semiconductor integrated circuit according to an embodiment includes a setting file storing unit having stored therein a list in which a scenario and a parameter used for verification are described and a transfer data generating unit configured to generate, on the basis of the list, transfer data used for the verification. The transfer data generating unit generates a tag in which information of the scenario is described.

Claims

1. A verification apparatus for a semiconductor integrated circuit comprising:

a setting file storage module having stored therein a list describing a scenario and a parameter used for verification of the semiconductor integrated circuit; and

a transfer data generation module configured to generate, based on the list, a tag describing transfer data used for verification and information about the scenario.

2. The verification apparatus for a semiconductor integrated circuit of claim 1, wherein the apparatus is further configured to selectively allow incorporation of the tag in the transfer data.

3. The verification apparatus for a semiconductor integrated circuit of claim 2, wherein the apparatus is further configured to specify a position of the tag in the transfer data.

4. The verification apparatus for a semiconductor integrated circuit of claim 3, wherein

the verification apparatus is configured to verify a multifunction semiconductor integrated circuit comprising a plurality of processors, and

wherein the tag comprises at least one identifier indicative of the processor executing the scenario and also indicative of the scenario.

5. The verification apparatus for a semiconductor integrated circuit of claim 1, wherein the tag is converted into a fixed length.

6. The verification apparatus for a semiconductor integrated circuit of claim 5, wherein the tag is converted into the fixed length using a hash function.

7. The verification apparatus for a semiconductor integrated circuit of claim 1, further comprising an expected value generation module configured to generate an expected value of data generated by a test program based on the list, when the test program is executed using the transfer data.

8. The verification apparatus for a semiconductor integrated circuit of claim 1, wherein

the verification apparatus is further configured to verify a multifunction semiconductor integrated circuit comprising a plurality of processors, and

wherein the tag comprises at least one identifier indicative of the processor configured to execute the scenario and also indicative of the scenario.

9. The verification apparatus for a semiconductor integrated circuit of claim 8, further comprising an expected value generation module configured to generate an expected value of data generated by a test program based on the list, when the test program is executed using the transfer data.

10. A verification method for a semiconductor integrated circuit by using a verification apparatus comprising:

reading a list comprising a scenario and a parameter used for verification of the semiconductor integrated circuit;

generating, based on the list, transfer data used for the verification;

generating, based on the the list, a tag comprising information about the scenario; and

executing a test program based on the list using the transfer data.

11. The verification method for a semiconductor integrated circuit of claim 10, further comprising selectively incorporating the generated tag in the transfer data.

12. The verification method for a semiconductor integrated circuit of claim 11, further comprising specifying a position of the tag in the transfer data.

13. The verification method for a semiconductor integrated circuit of claim 12, wherein

the tag comprises at least one identifier indicative of a processor executing the scenario and an identifier indicative of the executed scenario.

14. The verification method for a semiconductor integrated circuit of claim 10, wherein the tag is converted into a fixed length.

15. The verification method for a semiconductor integrated circuit of claim 14, wherein the tag is converted into the fixed length using a hash function.

16. The verification method for a semiconductor integrated circuit of claim 10, further comprising:

verifying a multifunction semiconductor integrated circuit comprising a plurality of processors,

wherein the tag comprises at least one identifier indicative of one of the plurality of processors executing the scenario and also indicative of the scenario.

17. The verification method for a semiconductor integrated circuit of claim 10, further comprising generating an expected value of data generated by a test program based on the list, when the test program is executed using the transfer data.

18. A verification apparatus for a semiconductor integrated circuit, comprising:

a setting file storage module having stored therein a scenario list comprising one or more scenarios used for verification of the semiconductor integrated circuit and a parameter list comprising one or more parameters; and

a transfer data generation module configured to generate, based on a scenario selected from the scenario list and further based on a parameter selected from the parameter list, transfer data used for the verification and a tag comprising information of the scenario.

19. The verification apparatus for a semiconductor integrated circuit of claim 18, further comprising:

a test program assembly module configured to generate a test program on the basis of the scenarios and the lists; and

an information storage module configured to store the test program, the transfer data, and the tag.

20. The verification apparatus for a semiconductor integrated circuit of claim 19, further comprising an expected value generating module configured to generate an expected value of data generated by the test program.