THIN FILM TRANSISTOR HAVING A TWO-LAYER SEMICONDUCTOR, MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS USING THE SAME

• US 20120132911A1
• Filed: 02/09/2012
• Published: 05/31/2012
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Shimada, Mikio, Hayashi, Ryo, Kumomi, Hideya
• Application Number:
  US13/369,406
• Publication Number:
  US 20120132911A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 33/0054 for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

Abstract

A transistor is constituted of a gate electrode 2, a gate insulation layer 3, a semiconductor layer 4 formed of an amorphous oxide, a source electrode 5, a drain electrode 6 and a protective layer 7. The protective layer 7 is provided on the semiconductor layer 4 in contact with the semiconductor layer 4, and the semiconductor layer 4 includes a first layer at least functioning as a channel layer and a second layer having higher resistance than the first layer. The first layer is provided on the gate electrode 2 side of the semiconductor layer 4 and the second layer is provided on the protective layer 7 side of the semiconductor layer 4.

Claims

1. A thin film transistor comprising a gate electrode, a gate insulation layer, a semiconductor layer formed of an oxide semiconductor, a source electrode, a drain electrode and a protective layer,

wherein the protective layer is provided on the semiconductor layer in contact with the semiconductor layer, and

wherein the semiconductor layer includes a first layer at least functioning as a channel layer and a second layer having higher resistance than the first layer, the second layer being provided on the protective layer side of the semiconductor layer, and the second layer has a mass density not larger than the mass density of the first layer.

2. The thin film transistor according to claim 1, wherein the second layer has a mass density not larger than 90% of the mass density in the crystal state of a material constituting the second layer.

3. The thin film transistor according to claim 1, wherein the semiconductor layer is formed of an amorphous oxide semiconductor containing at least one of In, Zn and Ga.

4. The thin film transistor according to claim 1, wherein the first layer is provided on the gate electrode side of the semiconductor layer.

5. The thin film transistor according to claim 1, wherein the semiconductor layer is oxidized more deeply than the depth of damage the semiconductor layer receives when the protective layer is formed.