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PLL START-UP CIRCUIT

  • US 20120133405A1
  • Filed: 11/25/2010
  • Published: 05/31/2012
  • Est. Priority Date: 11/25/2010
  • Status: Active Grant
First Claim
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1. A start-up circuit for a Phase locked loop (PLL), comprising;

  • a phase-frequency detector (PFD) for comparing the frequency of a reference signal with the frequency of a feedback signal to generate first and second comparison signals, wherein the feedback signal is an output signal generated by the PLL;

    one or more AND gates, connected to the PFD, for generating first and second intermediate signals using the first and second comparison signals;

    a first flip-flop, connected to the one or more AND gates, for transmitting the first intermediate signal to the output terminal of the first flip-flop based on the second intermediate signal, wherein the first intermediate signal is received at the data input terminal of the first flip-flop and the second intermediate signal is received at the clock input terminal of the first flip-flop;

    a set of second flip-flops, connected to the first flip-flop, for transmitting the first intermediate signal based on the reference signal, wherein the set of second flip-flops receives the first intermediate signal from the output terminal of the first flip-flop at the data input terminal and the reference signal at the clock input terminal; and

    an OR gate, connected to the first flip-flop and the set of second flip-flops, for generating a start-up signal based on the first intermediate signal received from the first flip-flop and from the set of second flip-flops.

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