Memory Modules and Devices Supporting Configurable Core Organizations

• US 20120134084A1
• Filed: 02/03/2012
• Published: 05/31/2012
• Est. Priority Date: 02/28/2001
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Hampel, Craig E., Perego, Richard E., Stark, Donald C.
• Granted Patent: US 8,412,906 B2
• Time in Patent Office: Days
• US Class Current: 361/679.01
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1087 : Data input latches
• CPC Class Codes: G11C 8/06 : Address interface arrangements, e.g. address buffers
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 1/14 : Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/09954 : More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
• CPC Class Codes: H05K 2201/10189 : Non-printed connector
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

Claims

1. (canceled)

2. A memory apparatus comprising:

an input to receive width selection information;

an interface to exchange data with a remote device;

a plurality of memory subsections, each subsection including columns of memory cells coupled to corresponding sense amplifiers; and

routing coupling the memory subsections with the interface, the routing supporting first and second width configurations responsive to the width selection information;

wherein

in the first width configuration, the routing conveys data of a first data width between a first integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a first memory depth, and

in the second width configuration, the routing conveys data of a second data width between a second integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a second memory depth;

wherein the memory apparatus loads the sense amplifiers in the first number of the memory subsections for read operations in the first width configuration and loads the sense amplifiers in the second number of memory subsections for read operations in the second width configuration.

3. The memory apparatus of claim 2, further comprising:

a command interface to receive memory commands, the memory commands including address information;

decode logic to receive and to decode the address information and the width selection information, to produce decoded information; and

routing control logic coupled between the decode logic and the routing to convey the decoded information to the routing.

4. The memory apparatus of claim 3, wherein the routing selects the first integer number or the second integer number responsive to the width selection information.

5. The memory apparatus of claim 2, wherein each memory subsection comprises a physical memory bank and the first and second integer numbers of the memory subsections respectively comprise a first logical bank and a second logical bank.

6. The memory apparatus of claim 2, wherein the first integer number is one.

7. The memory apparatus of claim 2, wherein the routing comprises a cross-bar switch.

8. The memory apparatus of claim 2, wherein the first number of the memory subsections has a first subsection width, the second number of the memory subsections has a second subsection width, and the ratio of the first data width to the first subsection width equals the ratio of the second data width to the second subsection width.

9. The memory apparatus of claim 2, embodied as a memory module.

10. The memory apparatus of claim 2, embodied as a computer motherboard.

11. The memory apparatus of claim 2, wherein the plurality of memory subsections collectively forms a reconfigurable memory core of a discrete integrated circuit device.

12. The memory apparatus of claim 2, wherein:

the memory apparatus further comprises first and second data lines;

in the first width configuration, data is conveyed on the first and the second data lines; and

in the second width configuration, data is conveyed on the first data line but not the second data line.

13. The memory apparatus of claim 12, wherein:

the memory apparatus further comprises first and second data pins;

the memory apparatus further comprises a crossbar switch coupling the first and second data pins with the first data line; and

the crossbar switch is to couple the first data line with a selective one of the first data pin or the second data pin.

14. The memory apparatus of claim 13, embodied as a dynamic random access memory device.

15. The memory apparatus of claim 2, wherein:

the routing coupling the memory subsections with the interface additionally supports a third width configuration responsive to the selection information; and

in the third width configuration, the routing conveys data of a third data width between a third integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provides a third memory depth.

16. The memory apparatus of claim 15, wherein:

the routing coupling the memory subsections with the interface additionally supports a fourth width configuration responsive to the selection information; and

in the fourth width configuration, the routing conveys data of a fourth data width between a fourth integer number of the memory subsections and the interface, and the plurality of memory subsections collectively provide a fourth memory depth.

17. The memory apparatus of claim 15, wherein each memory subsection is a physical memory bank, and wherein the first width configuration includes four logical banks, the second width configuration includes two logical banks, and the third width configuration includes one logical bank.

18. A memory controller, comprising:

an output to send width selection information to at least one variable-width memory;

a data interface having a width N for exchanging data with the at least one variable-width memory in a point-to-point configuration;

wherein

when the controller exchanges data with only a first variable-width memory, the width selection information comprises a memory width of N; and

when the controller exchanges data with the first variable-width memory and a second variable-width memory, the width selection information comprises a memory width of N/2.

19. The memory controller of claim 18, wherein the width selection information is halved when the memory controller senses the number of variable-width memories doubling.

20. The memory controller of claim 18, further comprising:

circuitry to detect the number of variable-width memories with which the memory controller exchanges data.

21. The memory controller of claim 19, further comprising:

circuitry to alter the width selection information in response to changes in the number of variable-width memories.