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INTEGRATED CIRCUIT HAVING MEMORY ARRAY INCLUDING ECC AND COLUMN REDUNDANCY, AND METHOD OF OPERATING SAME

  • US 20120134216A1
  • Filed: 11/29/2011
  • Published: 05/31/2012
  • Est. Priority Date: 06/26/2006
  • Status: Active Grant
First Claim
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1. An integrated circuit device comprising:

  • a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns;

    multiplexer circuitry, coupled to the memory cell array, wherein the multiplexer circuitry comprises a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data, and (ii) a second input to receive read data, and an associated output to responsively output data from one of the plurality of inputs; and

    syndrome generation circuitry, coupled to the multiplexer circuitry, to generate;

    (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.

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