INTEGRATED CIRCUIT HAVING MEMORY ARRAY INCLUDING ECC AND COLUMN REDUNDANCY, AND METHOD OF OPERATING SAME

• US 20120134216A1
• Filed: 11/29/2011
• Published: 05/31/2012
• Est. Priority Date: 06/26/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Singh, Anant Pratap
• Granted Patent: US 8,402,326 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G01J 2003/1213 Filters in general, e.g. dichroic, band
• CPC Class Codes: G01J 2003/2866 Markers; Calibrating of scan
• CPC Class Codes: G01J 3/02 Details
• CPC Class Codes: G01J 3/0291 Housings; Spectrometer accessories; Spatial arrangement of elements, e.g. folded path arrangements
• CPC Class Codes: G01J 3/10 Arrangements of light sources specially adapted for spectrometry or colorimetry
• CPC Class Codes: G01J 3/28 Investigating the spectrum using colour filters G01J3/51
• CPC Class Codes: G01N 2201/129 Using chemometrical methods
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

An integrated circuit device comprising a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory cell array, comprising a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data which is representative of data to be written into the memory cells of the memory cell array in response to a write operation, and (ii) a second input to receive read data which is representative of data read from memory cells of the memory cell array, and an associated output to responsively output data from one of the plurality of inputs; and syndrome generation circuitry, coupled to the multiplexer circuitry, to generate: (i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.

Claims

1. An integrated circuit device comprising:

a memory cell array comprising a plurality of memory cells arranged in a matrix of rows and columns;

multiplexer circuitry, coupled to the memory cell array, wherein the multiplexer circuitry comprises a plurality of data multiplexers, each data multiplexer having a plurality of inputs, comprising (i) a first input to receive write data, and (ii) a second input to receive read data, and an associated output to responsively output data from one of the plurality of inputs; and

syndrome generation circuitry, coupled to the multiplexer circuitry, to generate;

(i) a write data syndrome vector using the write data and (ii) a read data syndrome vector using the read data.

2. The integrated circuit device of claim 1 wherein the write data is representative of data to be written into memory cells of the memory cell array in response to a write operation.

3. The integrated circuit device of claim 1 wherein the read data is representative of data read from memory cells of the memory cell array in response to a read operation.

4. The integrated circuit device of claim 1 wherein the syndrome generation circuitry comprises a plurality of XOR logic gates.

5. The integrated circuit device of claim 4 wherein the plurality of XOR logic gates is arranged in a logic tree architecture comprising first, second and third levels of XOR logic, wherein:

the first level of XOR logic comprises inputs to receive the outputs of the plurality of data multiplexers;

the second level of XOR logic comprises inputs to receive the outputs of the first level of XOR logic; and

the third level of XOR logic comprises inputs to receive the outputs of the second level of XOR logic.

6. The integrated circuit device of claim 4 wherein the plurality of XOR logic gates is arranged in a logic tree architecture comprising a plurality of levels of XOR logic levels, wherein a Nth level of XOR logic comprises (i) inputs to receive the outputs of a preceding level of XOR logic gates and data from at least one redundant or spare column and (ii) an output that is the read data syndrome vector.

7. The integrated circuit device of claim 1 wherein:

the multiplexer circuitry further comprises a plurality of check bit multiplexers, each check bit multiplexer having a plurality of inputs, comprising (i) a first input to receive check bit data, and (ii) a second input to receive a predetermined data, and an associated output to responsively output data from one of the plurality of inputs; and

the syndrome generation circuitry generates;

(i) a write data syndrome vector using the write data and the predetermined value, and (ii) a read data syndrome vector using the read data and the check bit data.

8. The integrated circuit device of claim 7 wherein the syndrome generation circuitry comprises a plurality of XOR logic gates.

9. The integrated circuit device of claim 8 wherein the plurality of XOR logic gates is arranged in a logic tree architecture comprising first, second and third levels of XOR logic, wherein:

the first level of XOR logic comprises inputs to receive the outputs of the plurality of data multiplexers;

the second level of XOR logic comprises inputs to receive the outputs of the first level of XOR logic; and

the third level of XOR logic comprises inputs to receive the outputs of the second level of XOR logic.

10. The integrated circuit device of claim 8 wherein the plurality of XOR logic gates is arranged in a logic tree architecture comprising a plurality of levels of XOR logic levels, wherein a Nth level of XOR logic comprises (i) inputs to receive the outputs of a preceding level of XOR logic gates and data from at least one redundant or spare column and (ii) an output that is the read data syndrome vector.

11. The integrated circuit device of claim 1 wherein the write data syndrome vector is stored in memory as check bit data.

12. The integrated circuit device of claim 1 wherein the columns comprise (i) a plurality of normal columns which is selectable via normal column address data, and (ii) a redundant column which is selectable via a redundant column address data.

13. The integrated circuit device of claim 12 further comprising address converter circuitry, coupled to the syndrome generation circuitry, to generate defective column address data, which is representative of a physical bit location of a defective column, using the read data syndrome vector.

14. The integrated circuit device of claim 13 further comprising a defective column address memory, coupled to the address converter circuitry, to store the defective column address data.

15. The integrated circuit device of claim 14 wherein the memory permanently stores the defective column address data.

16. The integrated circuit device of claim 13 further comprising a plurality of redundancy program circuits that are coupled to the memory array to receive the read data and spare column data, which is representative of data read from memory cells associated with the redundant column of the memory cell array, wherein each redundancy program circuit outputs (i) read data which is associated with one of a normal column or (ii) the spare column data, and wherein when one of a normal column address data corresponds to the defective column address data, the redundancy program circuit associated therewith outputs the defective column address data.

17. The integrated circuit device of claim 16 wherein each redundancy program circuit comprises:

a multiplexer having a plurality of inputs, including (i) a first input to receive read data which is associated with one of a normal column, and (ii) a second input to receive the spare column data, and an associated output to responsively output data from one of the plurality of inputs; and

a memory, coupled to an associated multiplexer, to store spare column control data which controls the associated multiplexer.

18. The integrated circuit device of claim 17 wherein the memory of each redundancy program circuit is coupled to the address converter circuitry and, in response to a program signal, the memory of the redundancy program circuit which is associated with the normal column that corresponds to the defective column address data stores the spare column control data.

19. The integrated circuit device of claim 17 wherein the memory, in response to a program signal, stores the spare column control data.

20. The integrated circuit device of claim 16 further including a plurality of logic gates having a first input to receive an output of an associated redundancy program circuit and a second input to receive correction data wherein when the read data includes one or more errors therein, the one or more logic gates which receives read data having an error corrects the read data using the correction data.

21. The integrated circuit device of claim 20 wherein each logic gate of the plurality of logic gates includes an XOR logic gate.