SENSE AMPLIFIER AND SENSE AMPLIFIER LATCH HAVING COMMON CONTROL

• US 20120134226A1
• Filed: 08/18/2011
• Published: 05/31/2012
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Chow, Daniel C.
• Granted Patent: US 8,553,482 B2
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable signal that is distinct from a clock signal. Moreover, the latch enable signal of the sense amplifier latch may be controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier.

Claims

1. An apparatus, comprising:

a sense amplifier coupled to receive a differentially-encoded pair of bit line signals from a column of storage cells of an array and further coupled to receive a sense amplifier enable signal that is distinct from a clock signal, wherein a valid value of the pair of bit line signals is encoded with a voltage differential across the pair of bit line signals that is smaller than a voltage difference between a true logic zero and a true logic one;

a sense amplifier latch including a latch input, a latch output, and a latch enable signal, wherein the latch input is coupled to receive one or more data output signals from the sense amplifier, wherein during operation, in response to assertion of the latch enable signal, the sense amplifier latch opens to pass a value of the latch input to the latch output, and in response to deassertion of the latch enable signal, the sense amplifier latch closes to store the value of the latch input;

wherein during operation, in response to assertion of the sense amplifier enable signal, the sense amplifier is activated to convert the voltage differential across the pair of bit line signals into the one or more data output signals encoded using voltage values corresponding to the true logic zero or the true logic one;

wherein the latch enable signal is controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier.

2. The apparatus of claim 1, further comprising:

a plurality of logic gates that, during operation, detects assertion of one or more input signals and responsively asserts the sense amplifier enable signal; and

a self-timed loop circuit coupled to the plurality of logic gates and further coupled to receive the sense amplifier enable signal;

wherein during operation, the self-timed loop circuit detects assertion of the sense amplifier enable signal and, in response, causes the sense amplifier enable signal to deassert, such that assertion of the sense amplifier enable signal is frequency dependent and deassertion of the sense amplifier enable signal is self-timed.

3. The apparatus of claim 1, further comprising:

a plurality of logic gates that, during operation, detects assertion of one or more input signals and responsively asserts a word line driver enable signal, wherein assertion of the word line driver enable signal controls whether a row of storage cells of the array is activated; and

a self-timed word line kill circuit coupled to the plurality of logic gates and further coupled to receive a sense amplifier enable signal generated by the plurality of logic gates;

wherein individual ones of the storage cells of the row correspond to respective columns of the array, the array including a respective pair of bit line signals corresponding to each column, and wherein each individual one of the storage cells of the row, when activated in response to assertion of the word line driver enable signal, outputs a stored value via a respective pair of bit line signals of a corresponding column; and

wherein during operation, the self-timed word line kill circuit detects assertion of the sense amplifier enable signal and, in response, causes the word line driver enable signal to deassert, such that assertion of the word line driver enable signal is frequency dependent and deassertion of the word line driver enable signal is self-timed.

4. The apparatus of claim 1, further comprising a multiplexer that, during operation, selects one of a bypass input or a scan data input to generate a test data output, wherein the test data output encodes both a data value and a control value that causes the data value to be selected, wherein the sense amplifier latch is coupled to receive the test data output, and wherein in response to the control value of the test data output, the sense amplifier latch during operation overrides a stored data value with the data value encoded by the test data output, such that the sense amplifier latch outputs the data value received from the multiplexer instead of the stored data value.

5. A memory array, comprising:

a plurality of storage cells arranged as a plurality of rows and a plurality of columns;

a plurality of bit lines, including at least one respective bit line for each of the plurality of columns, wherein ones of the storage cells that occupy a given one of the columns are coupled to the at least one respective bit line corresponding to the given column;

a plurality of sense amplifiers, including a respective sense amplifier for each of the plurality of columns, wherein the at least one respective bit line corresponding to the given column is coupled to the respective sense amplifier corresponding to the given column;

a plurality of sense amplifier latches, including a respective sense amplifier latch for each of the plurality of columns, wherein a data output of the respective sense amplifier corresponding to the given column is coupled to the respective sense amplifier latch corresponding to the given column;

wherein each of the sense amplifiers is coupled to receive a corresponding sense amplifier enable signal that is distinct from a clock signal, wherein in response to assertion of the corresponding sense amplifier enable signal, the respective sense amplifier corresponding to the given column amplifies a signal transmitted by the at least one respective bit line corresponding to the given column;

wherein each of the sense amplifier latches is coupled to receive an amplified signal output by a respective one of the sense amplifiers;

wherein in response to assertion of the corresponding sense amplifier enable signal, the respective sense amplifier latch corresponding to the given column opens to receive the amplified signal output by the respective sense amplifier corresponding to the given column;

wherein in response to deassertion of the corresponding sense amplifier enable signal, the respective sense amplifier latch corresponding to the given column closes to store the amplified signal output by the respective sense amplifier corresponding to the given column.

6. The memory array of claim 5, wherein assertion of the sense amplifier enable signal is frequency dependent and deassertion of the sense amplifier enable signal is self-timed.

7. The memory array of claim 5, wherein for each of the plurality of columns, the at least one respective bit line comprises a respective pair of differentially-encoded bit lines.

8. The memory array of claim 5, further comprising a plurality of word lines respectively corresponding to the plurality of rows, wherein each of the word lines controls whether a corresponding one of the rows is activated, and wherein assertion of each of the word lines is frequency dependent and deassertion of each of the word lines is self-timed.

9. The memory array of claim 5, wherein the sense amplifier latches are further configured to selectively output either values received from respective sense amplifiers or test data received from a source external to the memory array.

10. An apparatus, comprising:

a sense amplifier that, during operation, is activated for evaluation in response to assertion of a sense amplifier enable signal that is distinct from a clock signal; and

a sense amplifier latch coupled to receive data output from the sense amplifier and to controllably latch the data in response to a latch enable signal, wherein the latch enable signal is controlled by the sense amplifier enable signal.

11. The apparatus of claim 10, wherein assertion of the sense amplifier enable signal is frequency dependent and deassertion of the sense amplifier enable signal is self-timed.

12. The apparatus of claim 10, wherein the sense amplifier enable signal is logically derived from one or more memory array control signals in combination with one or more clock signals.

13. The apparatus of claim 10, wherein the sense amplifier is coupled to a pair of differentially-encoded bit lines corresponding to a column of storage cells of a memory array.

14. The apparatus of claim 10, wherein the sense amplifier latch is further configured to selectively output either data output received from the sense amplifier or test data received from a source other than the sense amplifier.

15. The apparatus of claim 14, wherein the test data encodes both a data value and a control value that causes the sense amplifier latch to select the data value.

16. A method, comprising:

asserting a sense amplifier enable signal that is distinct from a clock signal;

in response to assertion of the sense amplifier enable signal, evaluating a bit line input of a sense amplifier and generating a sense amplifier output;

in response to assertion of the sense amplifier enable signal, receiving the sense amplifier output onto a storage node of the sense amplifier latch; and

in response to deassertion of the sense amplifier enable signal, retaining a value of the storage node such that further changes in the sense amplifier output do not affect the value of the storage node while the sense amplifier enable signal is deasserted.

17. The method of claim 16, further comprising:

evaluating a test data input that encodes a control value indicative of whether a data value encoded in the test data input should be selected; and

in response to determining that the control value indicates that the data value should be selected, outputting the data value from the sense amplifier latch instead of the value of the storage node.

18. The method of claim 16, wherein the bit line input comprises a pair of differentially-encoded bit lines corresponding to a column of storage cells of a memory array.

19. A microprocessor, comprising:

an instruction execution core that, during operation, executes instructions; and

one or more memory arrays that, during operation, store instructions, data operated on during execution of instructions, or state information used during execution of instructions;

wherein the one or more memory arrays comprise;

a sense amplifier that, during operation, generates a sense amplifier output dependent upon a bit line input in response to assertion of a sense amplifier enable signal that is distinct from a clock signal;

a sense amplifier latch that, during operation, receives the sense amplifier output onto a storage node of the sense amplifier latch in response to assertion of the sense amplifier enable signal;

wherein the sense amplifier latch, during operation and in response to deassertion of the sense amplifier enable signal, further retains a value of the storage node such that further changes in the sense amplifier output do not affect the value of the storage node while the sense amplifier enable signal is deasserted.

20. The microprocessor of claim 19, wherein assertion of the sense amplifier enable signal is frequency dependent and deassertion of the sense amplifier enable signal is self-timed.