METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS

• US 20120137074A1
• Filed: 11/29/2010
• Published: 05/31/2012
• Est. Priority Date: 11/29/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Daehyun, Kim, Changkyu, Lee, Victor W., Chhugani, Jatin, Satish, Nadathur Rajagopalan
• Granted Patent: US 9,727,471 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 9/3004 to perform operations on memory

Abstract

A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.

Claims

1. An apparatus comprising:

logic to execute an instruction to copy data from a source memory address to a destination memory address, wherein the instruction is to specify a memory hierarchy level of the destination memory address.

2. The apparatus of claim 1, wherein the logic to execute the instruction to copy the data from the source memory address to the destination memory address is to:

perform an unallocated load instruction to copy the data from the source memory address to a buffer, wherein the unallocated load instruction does not allocate a cache memory line to store the data; and

copy the data in the buffer to the destination memory address based at least in part on the specified memory hierarchy level of the destination memory address.

3. The apparatus of claim 2, wherein the logic to perform the unallocated load instruction to copy the data from the source memory address to the buffer is to:

determine whether the data of the source memory address is stored in one of one or more cache memories; and

in response to a determination that the data of the source memory address is stored in one of the one or more cache memories, copy the stored data of the source memory address in the determined cache memory to the buffer.

4. The apparatus of claim 3, wherein the logic to perform the unallocated load instruction to copy the data from the source memory address to the buffer is further to:

determine whether the data of the source memory address is stored in a main memory in response to a determination that the data of the source memory address is not stored in one of the one or more cache memories; and

copy the stored data of the source memory address in the main memory to the buffer in response to a determination that the data of the source memory address is stored in the main memory.

5. The apparatus of claim 4, wherein the logic to copy the data in the buffer to the destination memory address based at least in part on the specified memory hierarchy level of the destination memory address is to:

copy the data in the buffer to the destination memory address at the specified memory hierarchy level in response to a determination that a memory hierarchy level of the stored data in the determined cache memory or main memory is higher than or equal to the specified memory hierarchy level.

6. The apparatus of claim 5, wherein the logic to copy the data in the buffer to the destination memory address based at least in part on the specified memory hierarchy level of the destination memory address is to:

copy the data in the buffer to the destination memory address at the memory hierarchy level of the stored data in the determined cache memory or the main memory in response to a determination that the memory hierarchy level of the stored data in the determined cache memory or the main memory is lower than the specified memory hierarchy level.

7. The apparatus of claim 2, wherein the buffer comprises a register.

8. The apparatus of claim 1, wherein a width of the copied data comprises one of a byte width, 32 bytes width, 64 bytes width, 128 bytes width, and a vector register width.

9. A system comprising:

a memory module; and

a processor coupled with the memory module, wherein the processor is to execute an instruction to copy data from a source address to a stream buffer in a cache memory.

10. The system of claim 9, wherein the stream buffer comprises a contiguous memory portion of the cache memory.

11. The system of claim 9, wherein the instruction comprises a set memory hierarchy to store the copied data, and wherein the processor to execute the instruction to copy the data from the source address to the stream buffer in the cache memory is to:

perform an unallocated load instruction to copy the data from the source address to a buffer, wherein the unallocated load instruction does not allocate a cache memory line of the cache memory; and

copy the data in the buffer to the stream buffer in the cache memory based at least in part on the set memory hierarchy to store the copied data.

12. The system of claim 11, wherein the processor to perform the unallocated load instruction to copy the data from the source address to the buffer is to:

determine whether the data of the source address is stored in the cache memory; and

in response to a determination that the data of the source address is stored in the cache memory, copy the stored data of the source address in the cache memory to the buffer.

13. The system of claim 12, wherein the processor to perform the unallocated load instruction to copy the data from the source address to the buffer is further to:

determine whether the data of the source address is stored in the memory module in response to a determination that the data of the source address is not stored in the cache memory; and

copy the stored data of the source address in the memory module to the buffer in response to a determination that the data of the source address is stored in the memory module.

14. The system of claim 13, wherein the processor to copy the data in the buffer to the stream buffer in the cache memory based at least in part on the set memory hierarchy to store the copied data is to:

copy the data in the buffer to the stream buffer in the cache memory at the set memory hierarchy in response to a determination that a memory hierarchy of the stored data in the cache memory or memory module is higher than the set memory hierarchy.

15. The system of claim 14, wherein the processor to copy the data in the buffer to the stream buffer in the cache memory based at least in part on the set memory hierarchy to store the copied data is further to:

copy the data in the buffer to the stream buffer at the set memory hierarchy of the stored data in the cache memory or the memory module in response to a determination that the memory hierarchy of the stored data in the cache memory or the memory module is lower than the set memory hierarchy.

16. The system of claim 9, wherein the cache memory comprises one of a level one cache memory, a level two cache memory, and a level three cache memory.

17. The system of claim 9, wherein the cache memory is part of the processor.

18. A method comprising:

copying data from a source address to a stream buffer in a cache memory, wherein the stream buffer comprises a contiguous memory portion of the cache memory.

19. The method of claim 18, wherein copying the data from the source address to the stream buffer in the cache memory comprises:

performing an unallocated load instruction to copy the data from the source address to a buffer, wherein the unallocated load instruction does not allocate a cache memory line of the cache memory; and

copying the data in the buffer to the stream buffer in the cache memory based at least in part on a set memory hierarchy to store the copied data.

20. The method of claim 19, wherein performing the unallocated load instruction to copy the data from the source address to the buffer comprises:

determining whether the data of the source address is stored in the cache memory; and

in response to a determination that the data of the source address is stored in the cache memory, copying the stored data of the source address in the cache memory to the buffer.

21. The method of claim 20, wherein performing the unallocated load instruction to copy the data from the source address to the buffer further comprises:

determining whether the data of the source address is stored in a main memory in response to a determination that the data of the source address is not stored in the cache memory; and

copying the stored data of the source address in the main memory to the buffer in response to a determination that the data of the source address is stored in the main memory.

22. The method of claim 21, wherein copying the data in the buffer to the stream buffer in the cache memory based at least in part on the set memory hierarchy to store the copied data comprises:

copying the data in the buffer to the stream buffer in the cache memory at the set memory hierarchy in response to a determination that a memory hierarchy of the stored data in the cache memory or main module is higher than the set memory hierarchy.

23. The method of claim 22, wherein copying the data in the buffer to the stream buffer in the cache memory based at least in part on the set memory hierarchy to store the copied data further comprises:

copying the data in the buffer to the stream buffer at the memory hierarchy of the stored data in the cache memory or the main memory in response to a determination that the memory hierarchy of the stored data in the cache memory or the main memory is lower than the set memory hierarchy.

24. The method of claim 18, wherein the cache memory comprises one of a level one cache memory, a level two cache memory, and a level three cache memory.