System and Method for a Cache in a Multi-Core Processor

• US 20120137075A1
• Filed: 06/09/2010
• Published: 05/31/2012
• Est. Priority Date: 06/09/2009
• Status: Active Grant

• Current Assignee: Ubitium GmbH
• Original Assignee: Hyperion Core, Inc.
• Inventors: Vorbach, Martin
• Granted Patent: US 9,086,973 B2
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/271 Non-uniform cache access [NUCA] architecture
• CPC Class Codes: G06F 2212/50 Control mechanisms for virtual memory, cache or TLB
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.

Claims

1. A multi-core processor system, in particular a single-package multi-core processor system, comprising:

at least two processor cores, preferably at least four processor cores,

each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache,

a tree communication structure combining the multiple LEVEL-1 caches,

the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and

TAG information is associated to data managed within the tree, usable in the treatment of the data.

2. The single package multi-core processor according to claim 1, wherein at least some of the TAGs are used for implementing locks.

3. A processor system according to claim 1, further comprising

TAG information means for TAG information associated to the data managed within the tree.

4. The multi-core processor according to claim 1,

wherein each of the said at least two, preferably four cores are capable of accessing data in each others LEVEL-1 caches at runtime.

5. A processor, in particular according to claim 1, comprising

at least one processor core, and

a local memory, wherein

the local memory'"'"'s physical address space is defined by a window within the virtual address space.

6. The processor according to claim 5, wherein the local memory is a tightly coupled memory.

7. The single package multi-core processor according to claim 5, wherein the local memory is a locally coupled memory.

8. The single package multi-core processor according to claim 7, being adapted for checking access rights for accessing the physical address space of the local memory are checked.

9. A single package multi-core processor according to claim 1, comprising:

at least four processor cores,

each of said at least four cores having a local LEVEL-1 cache,

a tree communication structure combining the multiple LEVEL-1 caches,

the tree having nodes,

the processor cores with the respective local caches being leaves of the tree,

a LEVEL-2 cache being the root node of the tree or in communication therewith;

wherein each node checks whether a requested address is stored downstream the node, and

i) if the requested address is stored downstream the node, the request is sent down the tree and the according data is delivered from a downstream LEVEL-1 cache, or

ii) if the requested address is not stored downstream the node, it is requested from an upstream node.

10. The single package multi-core processor according to claim 9, wherein the highest level node requests addresses from the nearest LEVEL-2 cache, in case the requested address is not stored downstream the node.

11. The single package multi-core processor according to claim 8, wherein each address is only cached once in the cache structure, and data is delivered from the according cache to cores requesting the address.

12. The single package multi-core processor according to claim 8, processing software optimizing the locality of data in the LEVEL-1 cache vicinities during operation.

13. The single package multi-core processor according to any of claim 8, processing task or threads being optimized for keeping shared data local in vicinities of LEVEL-1 caches.

14. The single package multi-core processor according to any of claim 8, at least some of the nodes comprising a lookup table for referencing a requested address to the cache storing data related of the address.

15. The single package multi-core processor according to any of claim 8, wherein at least some of the nodes are capable of handling multiple transfers and/or accesses in parallel.

16. The single package multi-core processor according to any of claim 8, wherein at least some of the edges comprise a plurality of buses, the plurality of buses supporting a plurality of data transfers in parallel.

17. The single package multi-core processor according to any of claim 8, wherein an arbiter selects a free unused bus for a node or cache requesting a bus.

18. A cache system for multi-core processors,

each core having a closely coupled level 1 data cache, wherein

an address is cached only once within all level 1 caches of the processor;

at least some processors have access to the level 1 cache of at least one other processor for transmitting data;

the at least some processors having an extended cache tag structure for storing a reference between an address and the at least one other processor having the data of the respective address cached.

20. The cache system according to claim 18, wherein the level 1 caches are interconnected by a tree structure.

21. The cache system according to one of claim 18, wherein the move of the cache line is triggered by an access of a core being nominated as preferred owner.

22. The cache system according to one of claim 18, wherein the move of the cache line is triggered by counter reaching a threshold value.

23. The cache system according to claim 22, wherein threshold value is defined by at least one of the application software and the operating system and/or in response to signals provided therefrom.

24. The cache system according to claim 22, wherein threshold value is defined by the owner of the cache line and/or in response to signals provided therefrom.

19. A cache system for multi-core processors,

each core having a closely coupled level 1 data cache, wherein

an address is cached only once within all level 1 caches of the processor;

and

means to move the cache line related to an address from the cache of the core owning the cache line into the cache of the core requesting the address.

25. A method for operating level 1 caches in a multi-core processor, wherein

an address is cached only once within all level 1 caches of the processor;

and

the cache line related to an address is moved from the cache of the core owning the cache line into the cache of the core requesting the address.

26. The method according to claim 25, wherein the level 1 caches are interconnected by a tree structure.

27. The method according to one of claim 25, wherein the move of the cache line is triggered by an access of a core being nominated as preferred owner.

28. The method according to one of claim 25, wherein the move of the cache line is triggered by counter reaching a threshold value.

29. The method according to claim 28, wherein threshold value is defined by at least one of the application software and the operating system and/or in response to signals provided therefrom.

30. The method according to claim 28, wherein threshold value is defined by the owner of the cache line and/or in response to signals provided therefrom.

31. A single package multi-core processor comprising:

at least four processor cores,

each core having a local LEVEL-1 cache,

a tree communication structure combining the multiple LEVEL-1 caches,

the tree having nodes,

the processor cores with the respective local caches being leaves of the tree,

a LEVEL-2 cache being root node of the tree;

wherein at least some of the edges between the nodes comprise a plurality of buses being capable of handling multiple accesses and/or transfers in parallel.

32. The single package multi-core processor according to claim 31, wherein the at least some edges having of the plurality buses comprising an arbiter for allocating free buses for a requesting node or cache.

33. A single package multi-core processor comprising

at least four processor cores,

each core having a local LEVEL-1 cache,

a tree communication structure combining the multiple LEVEL-1 caches,

the tree having nodes,

the processor cores with the respective local caches being leaves of the tree,

a LEVEL-2 cache being root node of the tree;

wherein at least some of the node being capable of handling multiple accesses and/or transfers in parallel.

34. A single package multi-core processor comprising

at least two processor cores,

each core having a local LEVEL-1 cache,

a tree communication structure combining the multiple LEVEL-1 caches,

the tree having at least one node, and

TAG information is associated to the data managed within the tree, defining the treatment of the data.

35. The single package multi-core processor according to claim 34, wherein at least some of the TAGs are used for implementing locks.

36. A processor system comprising

at least two processor cores, and

TAG information is associated to the data managed within the tree, defining the treatment of the data.

37. The single package multi-core processor according to claim 36, wherein at least some of the TAGs are used for implementing locks.

38. A single package multi-core processor comprising

at least two processor cores,

each core having a local LEVEL-1 cache,

a tree communication structure combining the multiple LEVEL-1 caches,

the tree having at least one node, and

the cores being capable of accessing data in each others LEVEL-1 caches at runtime.

39. A single package processor comprising:

at least one processor core, and

a local memory;

wherein

the local memory'"'"'s physical address space is defined by a window within the virtual address space.

40. The single package multi-core processor according to claim 39, wherein at least some or all of the local memory is a tightly coupled memory.

41. The single package multi-core processor according to claim 39, wherein the local memory is a locally coupled memory.

42. The single package multi-core processor according to claim 39, wherein access rights for accessing the physical address space of the local memory are checked.