Disabling Communication in a Multiprocessor System

• US 20120137119A1
• Filed: 10/14/2011
• Published: 05/31/2012
• Est. Priority Date: 10/15/2010
• Status: Active Grant

• Current Assignee: Coherent Logix, Incorporated
• Original Assignee: Coherent Logix, Incorporated
• Inventors: Doerr, Michael B., Gibson, David A., Dobbs, Carl S., Solka, Michael B., Trocino, Michael R.
• Granted Patent: US 8,880,866 B2
• Time in Patent Office: Days
• US Class Current: 713/100
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 2221/034 Test or assess a computer or a system
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

Claims

1. A method for disabling communication in a multiprocessor fabric, the method comprising:

receiving a configuration for the multiprocessor fabric, wherein the multiprocessor fabric comprises a plurality of processors and a plurality of communication elements, wherein each of the plurality of communication elements comprises a memory, wherein the configuration specifies disabling of communication paths between one or more of;

one or more processors and one or more communication elements;

one or more processors and one or more other processors;

or

one or more communication elements and one or more other communication elements;

automatically configuring the multiprocessor fabric in hardware to disable the communication paths specified by the configuration;

operating the multiprocessor fabric to execute a software application, wherein the multiprocessor fabric operates according to the configuration.

2. The method of claim 1, said automatically configuring the multiprocessor fabric comprises setting register values corresponding one or more processors and/or one or more communication elements to disable the communication paths specified by the configuration.

3. The method of claim 1, wherein after said automatically configuring, the disabled communication paths are not restorable via software.

4. The method of claim 1, wherein the configuration specifies disabling of communication between a first portion of the multiprocessor fabric and a second portion of the multiprocessor fabric, wherein during operation, the first portion is isolated from the second portion.

5. The method of claim 1, wherein the configuration specifies disabling of memory access of a first portion of the multiprocessor fabric by a second portion of the multiprocessor fabric, wherein during operation, the second portion is unable to access memories comprised in the first portion.

6. The method of claim 1, further comprising:

loading encrypted code into the multiprocessor fabric, wherein the configuration is received from the encrypted code;

receiving a second configuration from the encrypted code; and

performing said automatically configuring based on the second configuration.

7. The method of claim 1, further comprising:

loading authenticated code into the multiprocessor fabric, wherein the configuration is received from the authenticated code;

receiving a second configuration from the authenticated code; and

performing said automatically configuring based on the second configuration.

8. The method of claim 1, further comprising:

loading encrypted and authenticated code into the multiprocessor fabric, wherein the configuration is received from the encrypted and authenticated code;

receiving a second configuration from the encrypted and authenticated code; and

performing said automatically configuring based on the second configuration.

9. The method of claim 1, wherein said receiving is performed automatically during a boot process of the multiprocessor fabric.

10. The method of claim 1, wherein the plurality of communication elements comprise dynamically configurable communication elements, each comprising a plurality of communication ports, a first memory, and a routing engine.

11. The method of claim 1, wherein, for each of the processors, a plurality of processor ports are configured for coupling to a first subset of the plurality of communication elements;

wherein, for each of the communication elements, a first subset of communication ports are configured for coupling to a subset of the plurality of processors and a second subset of communication ports are configured for coupling to a second subset of the plurality of communication elements.

12. The method of claim 1, wherein the plurality of processors and the plurality of communication elements are coupled together in an interspersed arrangement.

13. A system, comprising:

a multiprocessor fabric, wherein the multiprocessor fabric comprises a plurality of processors and a plurality of communication elements, wherein each of the plurality of communication elements comprises a memory;

configuration logic, wherein the configuration logic is configured to;

receive a configuration for the multiprocessor fabric, wherein the configuration specifies disabling of communication paths between one or more of;

one or more processors and one or more communication elements;

one or more processors and one or more other processors;

or

one or more communication elements and one or more other communication elements; and

automatically configure the multiprocessor fabric in hardware to disable the communication paths specified by the configuration, wherein after said automatically configuring, the disabled communication paths are not restorable via software;

wherein, after said configuring, the multiprocessor fabric is configured to execute a software application, wherein the multiprocessor fabric operates according to the configuration.

14. The system of claim 13, said automatically configuring the multiprocessor fabric comprises setting register values corresponding to one or more processors and/or one or more communication elements to disable the communication paths specified by the configuration.

15. The system of claim 13, wherein after said automatically configuring, the disabled communication paths are not restorable via software.

16. The system of claim 13, wherein the configuration specifies disabling of communication between a first portion of the multiprocessor fabric and a second portion of the multiprocessor fabric, wherein during operation, the first portion is isolated from the second portion.

17. The system of claim 13, wherein the configuration specifies disabling of memory access of a first portion of the multiprocessor fabric by a second portion of the multiprocessor fabric, wherein during operation, the second portion is unable to access memories comprised in the first portion.

18. The system of claim 13, wherein the configuration logic is configured to:

load encrypted code into the multiprocessor fabric, wherein the configuration is specified by the encrypted code;

receive a second configuration from the encrypted code; and

perform said automatically configuring based on the second configuration.

19. The system of claim 13, wherein the configuration logic is configured to:

load authenticated code into the multiprocessor fabric, wherein the configuration is specified by the authenticated code;

receive a second configuration from the authenticated code; and

perform said automatically configuring based on the second configuration.

20. The system of claim 13, wherein the configuration logic is configured to:

load encrypted and authenticated code into the multiprocessor fabric, wherein the configuration is specified by the encrypted and authenticated code;

receive a second configuration from the encrypted and authenticated code; and

perform said automatically configuring based on the second configuration.

21. The system of claim 13, wherein said receiving is performed automatically during a boot process of the multiprocessor fabric.

22. The system of claim 13, wherein each processor comprises at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports.

23. The system of claim 13, wherein each communication element comprises a dynamically configurable communication element, each comprising a plurality communication ports, a first memory, and a routing engine.

24. The system of claim 13, wherein, for each of the processors, a plurality of processor ports are configured for coupling to a first subset of the plurality of communication elements;

wherein, for each of the communication elements, a first subset of communication ports are configured for coupling to a subset of the plurality of processors and a second subset of communication ports are configured for coupling to a second subset of the plurality of communication elements.