METHOD AND APPARATUS FOR PERFORMING A MEMORY BUILT-IN SELF-TEST ON A PLURALITY OF MEMORY ELEMENT ARRAYS

• US 20120137185A1
• Filed: 11/30/2010
• Published: 05/31/2012
• Est. Priority Date: 11/30/2010
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Venkataramanan, Ganesh, Chen, Wei-Yu
• Application Number:
  US12/956,688
• Publication Number:
  US 20120137185A1
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence

Abstract

A method and apparatus are described for performing a memory built-in self-test (MBIST) on a plurality of memory element arrays. Control packets are output over a first ring bus to respective ones of the arrays. Each of the arrays receives its respective control packet via the first ring bus, and reads commands residing in a plurality of fields within the respective control packet. Each of the arrays performs at least one self-test based on the commands, and outputs a respective result packet over a second ring bus. Each result packet indicates the results of the self-test performed on the array. Each control packet is transmitted in its own individual time slot to a respective one of the arrays.

Claims

1. A method of performing a built-in self test on a plurality of units, the method comprising:

transmitting commands to the units over a first ring bus; and

responsive to and based on the transmitted commands, the units outputting results of tests performed on the units over a second ring bus.

2. The method of claim 1 wherein the units are memory element arrays.

3. The method of claim 1 wherein the commands reside in control packets.

4. The method of claim 3 wherein each control packet is transmitted in its own individual time slot to a respective one of the arrays.

5. The method of claim 3 wherein each control packet includes a control command field, a read command field and a write command field.

6. The method of claim 5 wherein the control command field indicates one of a background shift enable command, a compare enable command or a bit map enable command.

7. The method of claim 5 wherein the read command field indicates one of a read enable command, an inverse read command or a match command.

8. The method of claim 5 wherein the write command field indicates one of a write enable command, an inverse write enable command, or an initialization write command.

9. The method of claim 3 wherein each control packet includes a write port select field and a read port select field.

10. The method of claim 9 wherein the write port select field indicates the port bits selected for a write command, and the read port select field indicates the port bits selected for a read command.

11. The method of claim 3 wherein each control packet includes a read address field, a write address field and an array identifier field.

12. A built-in self-test interface device comprising:

a plurality of units;

a first bus over which commands are transmitted to the units; and

a second bus over which results of tests performed on the units are outputted in response to and based on the transmitted commands.

13. The built-in self-test interface device of claim 12 wherein the units are memory element arrays.

14. The built-in self-test interface device of claim 12 wherein the commands reside in control packets.

15. The built-in self-test interface device of claim 14 wherein each control packet is transmitted in its own individual time slot to a respective one of the arrays.

16. The built-in self-test interface device of claim 14 wherein each control packet includes a control command field, a read command field and a write command field.

17. The built-in self-test interface device of claim 14 wherein each control packet includes a write port select field and a read port select field.

18. The built-in self-test interface device of claim 14 wherein each control packet includes a read address field, a write address field and an array identifier field.

19. A computer-readable storage medium configured to store a set of instructions used for testing a semiconductor device, wherein the semiconductor device comprises:

a plurality of units;

a first bus over which commands are transmitted to the units; and

a second bus over which results of tests performed on the units are outputted in response to and based on the transmitted commands.

20. The computer-readable storage medium of claim 19 wherein the instructions are Verilog data instructions.

21. The computer-readable storage medium of claim 19 wherein the instructions are hardware description language (HDL) instructions.