SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES

• US 20120138886A1
• Filed: 12/01/2010
• Published: 06/07/2012
• Est. Priority Date: 12/01/2010
• Status: Active Grant

• Current Assignee: Sony Group Corp.
• Original Assignee: Intel Corporation
• Inventors: Kuhn, Kelin J., Kim, Seiyon, Rios, Rafael, Cea, Stephen M., Giles, Martin D., Cappellani, Annalisa, Rakshit, Titash, Chang, Peter, Rachmady, Willy
• Granted Patent: US 8,753,942 B2
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Claims

1. A method of forming a device comprising:

forming epitaxial silicon germanium on a substrate;

forming epitaxial silicon on the epitaxial silicon germanium;

patterning the epitaxial silicon disposed on the epitaxial silicon germanium to form fin structures;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers; and

removing one of the silicon and the epitaxial silicon germanium layers from the fin structures disposed between the spacers.

2. The method of claim 1 further comprising wherein the structure comprises a portion of a gate all around nanowire device.

3. The method of claim 1 further comprising forming additional alternating layers of epitaxial silicon germanium on epitaxial silicon.

4. The method of claim 1 further comprising wherein the silicon is removed from the fin structure to form silicon germanium nanowire structures separated from each other by a gap.

5. The method of claim 1 further comprising wherein the silicon germanium is removed from the fin structure to form silicon nanowire structures separated from each other by a gap.

6. The method of claim 4 further comprising wherein a gate dielectric is formed around all sides of the silicon germanium nanowire structures.

7. The method of claim 5 further comprising wherein a gate dielectric is formed around all sides of the silicon nanowire structures.

8. The method of claim 6 further comprising wherein a gate electrode material is formed around the silicon germanium nanowire structures.

9. The method of claim 7 further comprising wherein a gate electrode material is formed around the silicon nanowire structures.

10. The method of claim 8 further comprising wherein a gate electrode material is formed around the silicon germanium nanowire structures.

11. The method of claim 9 further comprising wherein the gate electrode material comprises metal.

12. The method of claim 10 further comprising wherein the gate electrode material comprises metal.

13. The method of claim 9 further comprising wherein a trench contact couples to the source drain structure, and wherein the source drain structure comprises n+ doped silicon.

14. The method of claim 13 further comprising wherein a silicon epitaxial tip is disposed between the source/drain structure and the substrate.

15. The method of claim 9 further comprising wherein the device comprises a portion of an NMOS gate all around channel device.

16. The method of claim 9 further comprising wherein a trench contact couples to the source drain structure, wherein the source/drain structure comprises p+ silicon germanium.

17. The method of claim 16 wherein a silicon epitaxial tip is disposed between the source drain structure and the substrate.

18. The method of claim 17 wherein the device comprises a portion of a PMOS gate all around channel device, and wherein the silicon nanowires comprises strained silicon nanowires.

19. A method of forming a nanowire device comprising:

forming alternating layers of epitaxial silicon on epitaxial silicon germanium on a SOI substrate;

patterning the alternating layers to form fin structures;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers; and

removing one of the silicon and the epitaxial silicon germanium layers from the fin structures disposed between the spacers.

20. The method of claim 19 further comprising wherein a bottom nanowire geometry of the fin structure is defined by controlling the etching of a bottom oxide portion of the SOI substrate.

21. The method of claim 20 further comprising wherein the bottom oxide is etched to form one nanowire and one trigate structure.

22. The method of claim 20 further comprising wherein the bottom oxide is etched to form two nanowires.

23. A method of forming a nanowire device comprising:

forming alternating layers of epitaxial silicon on epitaxial silicon germanium on a substrate;

forming fin structures by etching the alternating layers and forming trenches adjacent to the fin structures;

forming fin spacers on the fin structures;

performing a second trench etch to expose a bottom fin area of the fin structure;

oxidizing the bottom fin area;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers; and

removing the silicon layers from the fin structures disposed between the spacers.

24. The method of claim 23 further comprising wherein a bottom nanowire is disposed on the oxidized bottom fin area.

25. A method of forming a nanowire device comprising:

forming alternating layers of epitaxial silicon on epitaxial silicon germanium on a substrate;

forming fin structures by etching the alternating layers and forming trenches adjacent to the fin structures;

forming oxide in the trenches;

forming fin spacers on the fin structures;

oxidizing a bottom fin area;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, and then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers; and

removing the epitaxial silicon layers from the fin structures disposed between the spacers.

26. The method of claim 25 wherein a bottom nanowire is disposed on the oxidized bottom fin area.

27. A method of forming a nanowire device comprising:

forming alternating layers of an epitaxial semiconductor material on epitaxial oxide material on a substrate;

forming fin structures by etching the alternating layers;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers; and

removing a portion of the epitaxial oxide material from the fin structures disposed between the spacers.

28. The method of claim 27 wherein a bottom semiconductor material nanowire is disposed on the epitaxial oxide material.

29. The method of claim 27 wherein the epitaxial oxide is fully removed from the fin structures.

30. The method of claim 27 wherein the epitaxial oxide is partially removed from the fin structures.

31. A method of forming a nanowire device comprising:

forming alternating layers of an epitaxial silicon material on epitaxial silicon germanium material on a substrate;

forming fin structures by etching the alternating layers and forming trenches adjacent to the fin structures;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate;

filling a gap in the spacers that is adjacent to the fin structures with a second spacer;

forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers;

removing one of the silicon and the epitaxial silicon germanium layers from the fin structures disposed between the spacers.

32. The method of claim 31 wherein the second spacer material comprises at least one of a spacer like material and a low-k material.

33. The method of claim 31 further comprising wherein the gap in the spacers is filled on a source/drain side of the spacer.

34. The method of claim 31 further comprising wherein the gap in the spacers is filled on a gate side of the spacer.

35. A method of forming a nanowire device comprising:

forming alternating layers of an epitaxial silicon material on epitaxial silicon germanium material on a (100) substrate comprising a <

111>

channel;

forming fin structures by etching the alternating layers and forming trenches adjacent to the fin structures;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, and then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers;

removing the epitaxial silicon layers from the fin structures disposed between the spacers by using a wet etch that is selective to silicon and not to silicon germanium.

36. The method of claim 35 wherein silicon germanium nanowires are partially etched after removing all of the silicon between the SiGe nanowires of the fin structure.

37. The method of claim 36 wherein the wet etch comprises an anisotropic etch to minimize lateral etching within the spacers.

38. A method of forming a nanowire device comprising:

patterning alternating layers of nitride and oxide disposed on a silicon substrate to expose a back region and a trench region;

forming one of a silicon material and a silicon germanium material in the trench and back regions;

forming a hard mask on one of the silicon germanium and silicon;

forming a fin structure by removing a portion of the alternating layers of nitride and oxide not covered by the hard mask; and

forming nanowire structures by oxidizing the fin structure and then removing the oxidized portions.

39. The method of claim 38 further comprising wherein the nanowire structures are disposed across substantially all of the device.

40. A method of forming a nanowire device comprising:

patterning alternating layers of nitride and oxide disposed on a silicon substrate to expose a back region and a trench region;

forming one of a silicon material and a silicon germanium material in the trench and back regions;

forming a hard mask on one of the silicon germanium and silicon;

forming a forming a fin structure by removing a portion of the alternating layers of nitride and oxide not covered by the hard mask;

forming a second hard mask around the fin structure;

forming a gate region adjacent the fin structure, wherein a portion of the fin structure may be exposed;

forming nanowire structures by oxidizing the fin structure and then removing the oxidized portions.

41. The method of claim 40 further comprising wherein the nanowire structures are disposed only in the gate area.

42. The method of claim 40 further comprising wherein the oxidized portions of the fin structure is removed by:

etching the oxide with a wet etch; and

etching one of the silicon and silicon germanium with an anisotropic etch.

43. A nanowire device comprising:

a substrate;

a tall contact to couple with N and P nanowire channels;

a short contact coupled to one of the N and P nanowire channels, wherein the N and P nanowire channels are disposed above the substrate; and

a bottom contact disposed below the short contact coupled to one of the N and P nanowire channels and the substrate.

44. The structure of claim 43 wherein the substrate comprises N+ inverter comprising for Vss

45. The structure of claim 43 wherein the short contact and the bottom contact are misaligned to one another.

46. The structure of claim 43 wherein the N and P nanowires comprise left and right wing structures.

47. A nanowire device structure comprising:

nanowire channel structures disposed vertically over a gate region of a CMOS device, wherein the nanowire channel structures comprise one of silicon nanowire and a silicon germanium nanowire.

48. The structure of claim 47 wherein the nanowire channel structures comprise a first nanowire disposed vertically over a second nanowire.

49. The structure of claim 47 wherein the nanowire channel structures are disposed over substantially the entire device structure.

50. A nanowire device comprising:

a substrate comprising source/drain structures disposed adjacent spacers; and

nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

51. The nanowire device of claim 50 wherein the nanowire channel structures comprise epitaxial silicon nanowire channel structures that are separated from each other by a gap.

52. The nanowire device of claim 50 wherein the nanowire channel structures comprise epitaxial silicon germanium nanowire channel structures that are separated from each other by a gap.

53. The nanowire device of claim 50 further comprising wherein the nanowire channel structures comprises a gate dielectric material all around the nanowire channel structures, and a metal gate surrounding the nanowire channel structures.

54. The nanowire device of claim 50 further comprising wherein the gate dielectric material comprises a high k gate dielectric material.

55. The nanowire device of claim 50 further comprising wherein the nanowire channel structures comprise one of epitaxial silicon and epitaxial silicon germanium.

56. The nanowire device of claim 50 further comprising wherein the source/drain structures comprise epitaxial silicon germanium.

57. The nanowire device of claim 50 wherein the substrate comprises a SOI substrate, and a bottom nanowire channel structure is disposed on an oxide portion of the SOI substrate.

58. The nanowire device of claim 50 wherein the substrate comprises a SOI substrate, and a bottom nanowire channel structure is disposed on an oxide portion of the SOI substrate.

59. The nanowire device of claim 50 wherein the device comprises an NMOS device, wherein a trench contact is coupled to the source drain structures, wherein the source drain structures comprise n+ doped silicon, and wherein a silicon epitaxial tip is disposed between the source drain structures and the substrate.

60. The nanowire device of claim 50 wherein the device comprises a PMOS device, wherein a trench contact couples to the source drain structures, which comprises p+ doped silicon germanium, and wherein a silicon epitaxial tip is disposed between the source drain structures and the substrate 100.

61. The nanowire device of claim 50 wherein the nanowire channel structures comprise an epitaxial silicon germanium nanowire channel disposed on an epitaxial oxide nanowire channel structure.

62. The nanowire device of claim 61 wherein the epitaxial oxide nanowire is partially etched.