SEMICONDUCTOR DEVICE HAVING STACKED STRUCTURE INCLUDING THROUGH-SILICON-VIAS AND METHOD OF TESTING THE SAME

• US 20120138927A1
• Filed: 12/06/2011
• Published: 06/07/2012
• Est. Priority Date: 12/06/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KANG, Uk-song
• Application Number:
  US13/312,000
• Publication Number:
  US 20120138927A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device having a stacked structure including through-silicon-vias (TSVs) and a method of testing the semiconductor device. The semiconductor device includes a first semiconductor layer, one or more second semiconductor layers stacked on the first semiconductor layer, and a plurality of input through-silicon-vias (TSVs) to transmit signals from a plurality of input pads, respectively. In a test mode, a test signal from the plurality of input pads is transmitted through at least two test paths, and the test signal transmitted through each of the test paths is output as a test result with respect to each of the plurality of input TSVs through an output pad.

Claims

1. A semiconductor device comprising:

a first semiconductor layer;

one or more second semiconductor layers stacked on the first semiconductor layer; and

a plurality of input through-silicon-vias (TSVs) to transmit signals from a plurality of input pads, respectively,

wherein in a test mode, a test signal from the plurality of input pads is transmitted through at least two test paths, and the test signal transmitted through each of the test paths is output as a test result with respect to each of the plurality of input TSVs through an output pad.

2. The semiconductor device of claim 1, wherein the at least two test paths comprise:

a first test path formed in the first semiconductor layer and electrically insulated from the input TSVs; and

a second test path formed in the first semiconductor layer and electrically connected with the input TSVs through at least one node.

3. The semiconductor device of claim 2, wherein the first semiconductor layer comprises:

a path selecting unit to receive a first signal and a second signal through the first test path and the second test path, respectively, and to selectively output one of the first signal and the second signal; and

a first storing unit to receive and store the output of the path selecting unit,

wherein the path selecting unit and the first storing unit are disposed to correspond to each of the plurality of input TSVs.

4. The semiconductor device of claim 3, wherein during a first period, the path selecting unit selectively outputs the first signal and the first storing unit stores the first signal and outputs the first signal as the test result, and

during a second period, the path selecting unit selectively outputs the second signal and the first storing unit stores the second signal and outputs the second signal as the test result.

5. The semiconductor device of claim 3, wherein the at least two test paths further comprises a third test path to transmit the test signal through the input TSV.

6. The semiconductor device of claim 5, wherein the second semiconductor layer comprises a second storing unit to receive a third signal transmitted through the third test path and to store the third signal, and the second storing unit is disposed to correspond each of the plurality of input TSVs.

7. The semiconductor device of claim 6, wherein after the first signal and the second signal are output as the test results, the third signal is output as the test result.

8. The semiconductor device of claim 6, wherein at least one of the first storing unit and the second storing unit comprises:

a multiplexer comprising a first input end to receive a signal from one of the first through third test paths corresponding to an ath TSV and a second input end to receive a test result with respect to an (a−

1)th TSV; and

a latch to store an output of the multiplexer,

wherein a is an integer greater than 2.

9. The semiconductor device of claim 8, wherein at least one of the first storing unit and the second storing unit sequentially outputs a test result with respect to each of the plurality of input TSVs through the output pad bit-by-bit.

10. A semiconductor device comprising:

a first semiconductor layer;

one or more second semiconductor layers stacked on the first semiconductor layer; and

a plurality of output through-silicon-vias (TSVs) to transmit signals through a plurality of output pads, respectively,

wherein in a test mode, a test signal from a plurality of input pads is transmitted through at least two test paths, and the test signal transmitted through each of the test paths is output as a test result with respect to each of the plurality of output TSVs through the plurality of output pads.

11. The semiconductor device of claim 10, wherein the at least two test paths comprise:

a first test path formed in the first semiconductor layer and electrically insulated from the output TSVs; and

a second test path formed in the first semiconductor layer and electrically connected with the output TSVs through at least one node.

12. The semiconductor device of claim 11, wherein the first semiconductor layer comprises:

a path selecting unit to receive a first signal and a second signal through the first test path and the second test path and to selectively transmit the received first signal and the received second signal to the output pads,

wherein the path selecting unit is disposed to correspond to each of the plurality of output TSVs.

13. The semiconductor device of claim 12, wherein the at least two test paths further comprise a third test path to transmit the test signal through the output TSVs.

14. The semiconductor device of claim 13, wherein the second semiconductor layer comprises a first output control unit disposed on the third test path and to control application of a third signal, transmitted through the third test path, to the output TSVs.

15. The semiconductor device of claim 14, wherein the path selecting unit further receives a third signal, transmitted through the third test path, and selectively transmits the received third signal to the output pads.

16. A semiconductor device comprising:

a first semiconductor layer including an input pad to receive a test signal and an output pad to output the test signal;

a second semiconductor layer connected to the first semiconductor layer by at least one through-silicon-via (TSV); and

a path selecting unit to select at least one of a plurality of paths to transmit the test signal from the input pad to the output pad, wherein the plurality of paths include at least one path electrically insulated from the at least one TSV and at least one path electrically connected to the at least one TSV.

17. The semiconductor device of claim 16, wherein the at least one path electrically connected to the at least one TSV comprises:

at least one path through the at least one TSV; and

at least one path that is not through the at least one TSV.

18. The semiconductor device of claim 16, wherein the at least one TSV comprises:

an input TSV to transmit the test signal from the first semiconductor layer to the second semiconductor layer; and

a plurality of output TSVs to transmit the test signal from the second semiconductor layer to the first semiconductor layer.

19. The semiconductor device of claim 16, wherein the at least one TSV comprises:

a plurality of input TSVs to transmit the test signal from the first semiconductor layer to the second semiconductor layer; and

an output TSV to transmit the test signal from the second semiconductor layer to the first semiconductor layer.

20. The semiconductor device of claim 16, wherein the input pad receives the test signal from an external test unit and the output pad outputs the test signal to the external test unit.